Lead SoC Verification Engineer

TetraMem - Accelerate The World; Singapore; On-site; SGD 80,000 - 180,000; Full time

Job summary

TetraMem - Accelerate The World is seeking an experienced SoC verification engineer in Singapore to define test plans, build automation infrastructure, and develop reusable testbenches for block and system levels.

You will drive regression strategies, close coverage holes, and mentor junior engineers while collaborating with design teams to debug and resolve RTL and gate-level issues across RTL and post-P&R stages.

Qualifications

• MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree.
• In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology
• Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification
• Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding
• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core
• Experience in verifying designs at both of RTL level and post-P&R gate level
• Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Responsibilities

• Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
• Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels
• Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out
• Work with design engineers to debug and identify root causes of simulation failure
• Support test engineers for post-silicon validation
• Mentor and coach team members and junior engineers. Drive verification efficiency

Skills

UVM/OVM

Semiformal Verification

Assertion-based Verification

Hardware-Software Co-verification

Verilog/SystemVerilog

Python/Perl/TCL/Shell

C/C++

SystemC

ISAs Assembly Coding

MIPI/AMBA Bus Protocols

RISC-V/ARM/DSP Core

RTL & Post-P&R Verification

Education

MS in Electrical/Computer Engineering, CS or related (8+ years) or PhD (3+ years)

Tools

Testbench Environments

Job description

TetraMem - Accelerate The World is seeking an experienced SoC verification engineer in Singapore to define test plans, build automation infrastructure, and develop reusable testbenches for block and system levels.

You will drive regression strategies, close coverage holes, and mentor junior engineers while collaborating with design teams to debug and resolve RTL and gate-level issues across RTL and post-P&R stages.