DRAM Innovation Lead: Novel Channels & Interconnects

Brightecs Innovation Pte Ltd; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

Brightecs Innovation Pte. Ltd. (BIP) is seeking a senior DRAM memory architect to lead architecture and technology development for next‑generation DRAM memory and channel oxide materials.

The role requires coordinating multi-disciplinary teams across circuit, device, firmware, verification, and testing to deliver scalable, reliable memory solutions. Ideal candidates will have 8+ years in DRAM memory development, a strong fabrication- and research-driven background, and proven publication history

Qualifications

• Master's degree or above (PhD preferred).
• Major: Physics, materials science & engineering, chemistry.
• 8+ years of DRAM memory development experience, including at least 5 years as architecture or key technology lead.
• Familiar with TLC/QLC/PLC multi-bit memory mechanisms and their challenges to read/write algorithms, ECC, and wear leveling.
• Excellent systems thinking and cross-domain integration capabilities, able to efficiently coordinate circuit, device, firmware, verification, testing, and product teams.
• Excellent technical documentation writing and technical decision-making communication skills.
• In-depth understanding of the ECC architecture (BCH/LDPC) and DRAM controller collaboration mechanism is preferred.
• Familiarity with the impact of reliability modeling under advanced processes (such as TDDB, HCI, RTN) on the architecture.
• Publication of DRAM-related papers at international conferences (such as ISSCC, VLSI, IMW) is a plus.

Skills

Systems thinking

Cross-domain integration

Technical communication

Technical writing

Education

Master's degree or above

PhD preferred

Major: Physics, materials science & engineering, chemistry

Job description

Brightecs Innovation Pte. Ltd. (BIP) is seeking a senior DRAM memory architect to lead architecture and technology development for next‑generation DRAM memory and channel oxide materials.

The role requires coordinating multi-disciplinary teams across circuit, device, firmware, verification, and testing to deliver scalable, reliable memory solutions. Ideal candidates will have 8+ years in DRAM memory development, a strong fabrication- and research-driven background, and proven publication history