Campus Singapore-RTL Design Engineer (Memory & Interconnect)

Canaan Inc.; Singapore; Presencial; SGD 60.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

1:1 mentorship from senior experts

unrestricted access to AI tools

Work on world-class AI chips

Join core projects from day one

Descripción de la vacante

Canaan Inc. is seeking a Master's or higher educated engineer to contribute to the digital IC front-end flow with AI-assisted tools. The role involves RTL implementation for memory subsystems, microarchitecture iteration, and performance analysis, with opportunities in pre-simulation verification and C model development.

Strong learning ability, basic Verilog/SystemVerilog skills, and good English communication are valued, with mentorship and access to leading AI tools offered from day one.

Formación

• Master's or above in Electronics, Computer Science, or related fields.
• Basic Verilog/SystemVerilog and digital circuit fundamentals.
• No prior experience required; digital IC project experience is a plus. Learning ability, logical thinking, and technical potential are valued more.

Responsabilidades

• Use AI tools across the front-end flow and integrate automated agents in design flows.
• Drive microarchitecture design, iteration, and RTL implementation for memory subsystems and data movement.
• Perform functional evaluation and performance analysis; support pre-simulation verification.
• Join full front-end flow with AI agents, block-level microarchitecture/RTL, and C model build/test for architecture exploration.

Conocimientos

Verilog/SystemVerilog

Digital logic fundamentals

Learning ability & problem solving

English communication

Educación

Master's degree or above in Electronics/CS

Herramientas

AI tools for coding/verification

Descripción del empleo

• Use AI tools across the digital IC front-end flow; integrate automated agents into design flows and continuously optimize.
• Drive microarchitecture design, iteration, and RTL implementation for memory subsystems and data movement.
• Perform functional evaluation and performance analysis; support pre-simulation verification.

Requirements

• Master's or above in Electronics, Computer Science, or related fields.
• Basic Verilog/SystemVerilog and digital circuit fundamentals.
• No prior experience required; digital IC project experience is a plus. Learning ability, logical thinking, and technical potential are valued more.

Preferred

• Knowledge/experience in memory controllers (DDRC, HBM_Ctrl, 3DDRAM), interconnect (NoC), or AI chips.
• Good communication, teamwork, and fluent English.
• AI enthusiast who actively uses AI tools for coding and verification; curious and adaptable to new flows, including LPU dataflow chips.

What We Offer

• 1:1 mentorship from senior experts; unrestricted access to world-leading AI tools; work on world-class AI chips.
• Join core projects from day one: full front-end flow with AI agents, block-level microarchitecture/RTL, and C model build/test for architecture exploration.