Design Verification Engineer (AI/GPU/CPU)

EQ Semi; Saudi Arabia; On-site; SAR 111,600 - 167,400; Full time

Job summary

EQ Semi is seeking a Design Verification Engineer in Saudi Arabia to ensure the functional correctness of complex SoCs across AI, GPU, and CPU domains. The successful candidate will develop UVM-based testbenches, run formal and simulation-based verification, and drive coverage closure. Candidates should have at least 5 years of experience in digital verification and possess strong skills in SystemVerilog, scripting, and tools like VCS or Questa.

Qualifications

• 5+ years in digital verification.
• Proficiency in UVM, SystemVerilog, and scripting languages.
• Experience with simulation tools (VCS, Questa, etc.).

Responsibilities

• Develop testbenches and verification plans for complex SoCs.
• Use UVM, SystemVerilog, and formal verification tools.
• Debug simulation failures and improve coverage metrics.
• Collaborate with design and architecture teams to ensure functional correctness.

Skills

Digital verification

SystemVerilog

UVM

Scripting

Tools (VCS, Questa)

Education

BS/MS in Electrical Engineering or Computer Engineering

Tools

VCS

Questa

Job description

We are looking for a Design Verification Engineer to ensure functional correctness of complex SoCs across AI, GPU, and CPU domains. You’ll develop UVM-based testbenches, run formal and simulation-based verification, and drive coverage closure. Candidates should have 5+ years of experience in digital verification, with strong skills in SystemVerilog, scripting, and tools like VCS or Questa.

Qualifications

BS/MS in Electrical Engineering or Computer Engineering

5+ years in digital verification.

Proficiency in UVM, SystemVerilog, and scripting languages.

Experience with simulation tools (VCS, Questa, etc.)

Key Responsibilities

Develop testbenches and verification plans for complex SoCs.

Use UVM, SystemVerilog, and formal verification tools.

Debug simulation failures and improve coverage metrics.

Collaborate with design and architecture teams to ensure functional correctness.