Senior Validation Manager - High-Speed Analog IP

Synopsys; Porto Salvo; Presencial; EUR 70 000 - 100 000; Tempo integral

Resumo da oferta

Synopsys in Lisbon is seeking a Senior Validation Manager to lead a team focused on high-speed analog IP validation. You will oversee test plans, debugging, and reporting, guiding engineers to deliver robust validation results and collaborating with design, applications, and product teams to meet development schedules.

The role requires 5+ years in silicon validation, strong leadership, and expertise in SerDes, high-speed IP, and lab instrumentation.

Qualificações

• Minimum 5+ years in silicon validation, test, or characterization of analog or mixed-signal ICs.
• Experience managing technical teams, planning, resource allocation, and performance reviews.

Responsabilidades

• Lead silicon validation operations for high-speed analog ICs at Lisbon site, managing lab resources and test execution.
• Direct testing and characterization of SerDes implementations using precision equipment.
• Oversee silicon debug, identify root causes, and guide design teams.
• Develop comprehensive validation reports documenting silicon performance and compliance.
• Supervise design, fabrication, and bring-up of custom test boards and fixtures.
• Mentor and develop the validation engineering team, including training and performance management.
• Collaborate with analog/digital design, applications, and product management to resolve technical challenges.
• Maintain and enhance lab infrastructure to ensure equipment availability for validation activities.

Conhecimentos

Team leadership

Test automation

SerDes validation

High-speed analog IP

Python

MATLAB

English communication

Formação académica

Electronic Engineering

Electrical Engineering

Ferramentas

Oscilloscopes

Bit error rate testers

Network analyzers

Verilog

VHDL

Python

MATLAB

FPGA-based test systems

Descrição da oferta de emprego

Synopsys in Lisbon is seeking a Senior Validation Manager to lead a team focused on high-speed analog IP validation. You will oversee test plans, debugging, and reporting, guiding engineers to deliver robust validation results and collaborating with design, applications, and product teams to meet development schedules.

The role requires 5+ years in silicon validation, strong leadership, and expertise in SerDes, high-speed IP, and lab instrumentation.