Principal Post-Silicon Applications Engineer

Synopsys Inc; Viseu; Presencial; EUR 70 000 - 100 000; Tempo integral

Resumo da oferta

Synopsys Inc. in Porto Salvo, Portugal is seeking a Senior Post‑Silicon Applications Engineer to lead on-site silicon bring-up and production support for PCIe 6.0/7.0.

You will perform root-cause analysis across analog, digital, and system levels, collaborate with design and firmware teams, and develop robust test methodologies for SerDes validation. Willing to travel ~twice yearly.

Qualificações

• Bachelor's or Master's in Electrical Engineering with 10+ years in post-silicon validation or SerDes bring-up.
• Expertise with PCIe 6.0/7.0, PAM4 signaling, FLIT mode, and 64 GT/s protocols.
• Experience using high-bandwidth lab equipment for signal integrity analysis.

Responsabilidades

• Provide senior-level technical support during silicon bring-up and production phases for PCIe 6.0/7.0.
• Lead root cause analysis across analog, digital and system integration layers.
• Use high-bandwidth instruments to perform precision measurements and isolate failures at 64 GT/s+.
• Analyze Verilog/SystemVerilog RTL to diagnose digital design issues impacting silicon behavior.
• Collaborate with design and firmware teams to resolve PAM4 encoding and link training issues.
• Develop robust test methodologies and best practices for SerDes validation.

Conhecimentos

PCIe 6.0/7.0

Signal integrity

Verilog/SystemVerilog

Lab equipment proficiency

Root cause analysis

Formação académica

Bachelor's or Master's in Electrical Engineering

Ferramentas

Oscilloscopes

Bit error rate testers

Vector network analyzers

Protocol analyzers

Descrição da oferta de emprego

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are You are a senior technical expert who is called upon when PCIe 6.0 or 7.0 silicon exhibits unexpected behavior under critical timelines. Over the past decade, you have developed deep expertise in diagnosing complex issues that span analog signal integrity, digital protocol implementation, and system-level interoperability, often working with incomplete information and demanding schedules. Your knowledge of PCIe link training at 64 GT/s extends beyond theory into practical application. You understand where PAM4 encoding can obscure margining issues, where FLIT mode negotiation may encounter difficulties, and how subtle impedance discontinuities can compromise bring-up success.

Your experience debugging customer systems has given you the ability to identify power delivery issues from oscilloscope measurements and recognize when firmware assumptions conflict with hardware implementation. Leading technical discussions with customer architects and internal design teams is a natural extension of your work because you have established credibility through consistent results and deep technical knowledge.

You operate effectively without requiring exhaustive documentation, developing test plans, executing them, adapting as needed, and documenting findings to benefit future engineers. Traveling approximately twice annually to customer sites or internal laboratories is an expected aspect of the role, and you recognize that on-site presence often accelerates resolution significantly. At Synopsys, you will work with the most advanced SerDes IP in the industry, and your contributions will directly influence what our customers bring to market.

What You'll Be Doing

Provide senior-level technical support to customers during silicon bring-up and production phases for PCIe 6.0, PCIe 7.0, including on-site engagement when critical issues require direct technical presence

Lead comprehensive root cause analysis for complex signal integrity, protocol compliance, and interoperability challenges across analog, digital, and system integration layers

Utilize advanced laboratory instrumentation including high-bandwidth oscilloscopes, real-time spectrum analyzers, bit error rate testers, vector networkanalyzers, and protocol analyzers to perform precision measurements and isolate failure mechanisms at 64 GT/s and higher data rates

Analyze and simulate Verilog/SystemVerilogRTL, collaborating with digital design and firmware teams to resolve issues involving PAM4 encoding, FLIT mode operation, and link training state machine behavior

Drive technical engagements with customer engineering teams and system architects, translating technical findings into clear recommendations and design guidance

Develop and refine test methodologies, debug procedures, and technical best practices for next-generation SerDes validation and customer deployment

Travel approximately twice per year to customer locations or internal development sites for critical bring-up support and technical collaboration

The Impact You Will Have

Enable customer tape-outs and production ramps by resolving technical blockers that would otherwise delay significant development programs

Establish Synopsys as a recognized technical authority in PCIe 6.0/7.0 through substantive customer partnerships and effective technical problem resolution

Provide real‑world silicon and system‑level insightstoIP design, validation, and product development teams, improving quality and reducing time-to-market for future releases

Reduce costly silicon re‑spins by identifying and resolving subtle issues during initial bring‑up phases that would otherwise manifest in volume production

Develop the technical capabilities of applications and validation engineers across the organization through knowledge transfer and mentorship

Contribute to the technical roadmap for SerDes applications engineering by identifying opportunities to improve tooling, processes, and support infrastructure

Build enduring customer relationships that result in design wins and expanded IP adoption across next‑generation semiconductor platforms

What You'll Need

Bachelor's orMaster's degree in Electrical Engineering, Electronics Engineering, or related discipline with 10+ years of hands‑on experience in post‑silicon validation, applications engineering, or SerDes bring‑up

Extensive expertise with PCIe 6.0 or newer standards, including PAM4 signaling, FLIT mode operation, link training protocols, and compliance testing at 64 GT/s and above

Demonstrated proficiency using advanced laboratory equipment including high-bandwidth oscilloscopes, real‑time spectrum analyzers, bit error rate testers, vector network analyzers, and protocol analyzers for signal integrity and protocol debug

Experience analyzing and simulating Verilog orSystemVerilogRTL to diagnose digital design issues affecting silicon behavior

Solid understanding of high‑speed printed circuit board design, signal integrity principles, power delivery architectures, and system‑level integration is highly valuable

Willingness to travel approximately twice per year for on‑site customer support and internal technical collaboration

Who You Are

You approach complex technical failures systematically, pursuing root cause understanding rather than symptomatic resolution, and maintain focus until the underlying issue is fully characterized

You can engage effectively with senior customer architects, present technical data and analysis clearly, and establish credibility through demonstrated expertise and professional communication

You transition effectively between laboratory work, RTL analysis, customer interactions, and internal design reviews, maintaining context and priorities across multiple concurrent activities

You produce clear, well‑structured technical documentation and debug reports that enable both customers and internal teams to make informed decisions efficiently

You take ownership of ambiguous technical challenges, define appropriate resolution paths, and coordinate with relevant stakeholders without requiring external direction

You develop the capabilities of less experienced engineers through structured knowledge transfer, demonstrating analytical approaches and technical problem‑solving methods

The Team You'll Be Part Of Join a dynamic, highly skilled multi‑site team of Applications Engineers and IP integration specialists at Synopsys. The team partners closely with customers across the globe, providing technical expertise and integration support for industry‑leading Interface IP. Collaboration, knowledge sharing, and a commitment to solving hard problems are at the core of our team culture. Together, we enable our customers to deliver breakthrough semiconductor solutions that set new benchmarks for performance and reliability.

Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings.

Principal Post‑Silicon Applications Engineer Porto Salvo, Portuguese Republic, PT