Senior SystemVerilog/UVM Verification Engineer

Square One Resources; Polska; Hybrid; PLN 180,000 - 260,000; Full time

Job summary

Square One Poland is seeking a Senior Verification Engineer to join our client’s project, focusing on UVM/SystemVerilog verification for complex hardware IPs.

You will design and implement verification environments from the ground up, build drivers, monitors, scoreboards and coverage models, integrate VIPs for PCIe, DDR and AXI, and collaborate with hardware and software teams to ensure robust functional coverage.

Qualifications

• At least 5 years of verification experience.
• Proven ability to build verification environments from the ground up.
• Experience with UVM and SystemVerilog.
• Strong knowledge of Verification IPs and industry-standard protocols, including PCIe, DDR, and AXI.

Responsibilities

• Perform the full range of functional verification activities.
• Develop verification environments from scratch, including drivers, monitors, scoreboards, and coverage models.
• Integrate Verification IPs (VIPs) for protocols such as DDR, PCIe, and AXI.
• Define and implement verification sequences for complex control-flow scenarios.
• Gain a system-level understanding of products with strong hardware-software interaction.
• Integrate and maintain reference models.

Skills

UVM

SystemVerilog

Verification IPs

PCIe

DDR

AXI

C/C++/Python

Job description

Square One Poland is seeking a Senior Verification Engineer to join our client’s project, focusing on UVM/SystemVerilog verification for complex hardware IPs.

You will design and implement verification environments from the ground up, build drivers, monitors, scoreboards and coverage models, integrate VIPs for PCIe, DDR and AXI, and collaborate with hardware and software teams to ensure robust functional coverage.