Senior Hardware Design Engineer – NoC/IP Architect

Arteris; Kraków; On-site; PLN 180,000 - 320,000; Full time

Job summary

Arteris is seeking a Staff Hardware Design Engineer in Krakow to lead design and development of advanced hardware blocks for configurable IPs and NoC solutions. You will direct RTL coding, verification strategies, and optimize performance while collaborating with cross‑functional teams to ensure timely delivery.

You will mentor peers, shape architecture specifications, and engage with customers during technical discussions, leveraging your deep experience in SoC/IP design flows and industry

Qualifications

• 8–12 years of experience in SoC/IP/NoC design.
• Expertise in coherent and non‑coherent communication protocols (AMBA, AXI, ACE, PCIe, CXL, CHI, etc.).
• Strong understanding of CPU architectures (ARM/RISC‑V), cache systems, and memory coherence.
• Deep experience in SoC/IP design flow (specification, architecture, RTL, verification, synthesis, DFT, timing, power).

Responsibilities

• Design and develop complex hardware blocks for configurable IPs, including RTL coding and performance optimization.
• Define architecture specifications for NoC components and propose improvements.
• Develop verification environments and define functional coverage strategies.
• Resolve complex technical problems and provide support to team members.
• Collaborate with hardware, software, and verification teams for cohesive integration.
• Contribute to the evolution of team design and verification methodologies.
• Participate in technical discussions with customers and the application engineering team.
• Document designs and mentor less experienced engineers.

Skills

Verilog/SystemVerilog

C++

Python

SystemC

Fluent English

Education

Master's degree in electrical engineering or related field

Tools

Cadence

Synopsys

Mentor

Job description

Arteris is seeking a Staff Hardware Design Engineer in Krakow to lead design and development of advanced hardware blocks for configurable IPs and NoC solutions. You will direct RTL coding, verification strategies, and optimize performance while collaborating with cross‑functional teams to ensure timely delivery.

You will mentor peers, shape architecture specifications, and engage with customers during technical discussions, leveraging your deep experience in SoC/IP design flows and industry