Emulation Engineer: SoC Interconnect & Verification

Arteris; Kraków; On-site; PLN 147,000 - 178,000; Full time

Job summary

Arteris is seeking an Emulation Engineer in Kraków, Poland. You will design and deliver interconnect and memory hierarchy solutions for mobile, telecom, automotive and consumer SoCs. You’ll work with an expert team to create high-quality, configurable emulation solutions blending RTL with software.

You will influence development environments, architecture, verification, and methodologies, collaborating across business units to ensure performance and quality. English fluency is required.

Qualifications

• 3+ years’ experience in SoC integration or IP RTL design.
• Fluency in Verilog/SystemVerilog.
• Experience with Palladium, Veloce, or Zebu emulation platforms.
• Knowledge of ARM CHI-E/ACE/AXI bus protocols.
• Strong signal waveform debugging skills.
• Professional English communication.

Responsibilities

• Maintain hardware emulation system in operation.
• Define and execute emulation processes for projects.
• Integrate emulation with software platforms.
• Triaging regressions and debugging RTL.
• Improve emulation methodologies and metrics.
• Collaborate with design and validation teams.

Skills

Verilog

SystemVerilog

ARM CHI-E/ACE/AXI

English proficiency

Waveform debugging

Education

MS in EE/CS

BS in EE/CS

Tools

Palladium

Veloce

Zebu

Job description

Arteris is seeking an Emulation Engineer in Kraków, Poland. You will design and deliver interconnect and memory hierarchy solutions for mobile, telecom, automotive and consumer SoCs. You’ll work with an expert team to create high-quality, configurable emulation solutions blending RTL with software.

You will influence development environments, architecture, verification, and methodologies, collaborating across business units to ensure performance and quality. English fluency is required.