Senior Physical Verification Engineer — PV Decks & Automation

Silicon Labs Careers; Hyderabad City Taluka; On-site; PKR 1,800,000 - 3,000,000; Full time

Benefits offered by this job

Equity Rewards (RSUs)

Employee Stock Purchase Plan (ESPP)

Insurance plans with Outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs is seeking a senior CAD PV engineer to support design and layout teams, develop and QA PV rule decks, and collaborate across CAD, ESD, design and foundry groups. The role emphasizes debugging PV issues, implementing rule decks, and driving improvement through tooling benchmarks.

You will work with external vendors, perform impact analyses, and contribute to robust PV flows in a fast-paced embedded tech environment.

Qualifications

• 5+ years of related professional experience.
• Proficiency in developing and supporting DRC rule decks including custom rules in Calibre SVRF or similar languages.
• Experience in coding LVS, extraction and PERC rule decks is a plus.
• Experience with design/layout engineers for debugging PV issues.
• Scripting skills in PERL/Python/Shell for custom tooling.

Responsibilities

• Support design and layout teams to resolve PV issues during design cycles.
• Develop and QA PV rule decks (DRC, Dummy fill, Antenna, custom decks).
• Drive impact analysis meetings with stakeholders for deck updates.
• Collaborate with CAD, ESD, Design, Layout, Packaging and foundry teams to collect requirements.
• Conduct code reviews and create QA test cases for rule decks.
• Develop and maintain PV flows and methodologies to improve quality and performance.
• Evaluate new tools/features and benchmark them against existing flows.
• Collaborate with external vendors to report and track bugs.

Skills

Physical Verification

Python scripting

Communication

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Calibre SVRF

LVS

PERC

Calibre RVE

Virtuoso

Job description

Silicon Labs is seeking a senior CAD PV engineer to support design and layout teams, develop and QA PV rule decks, and collaborate across CAD, ESD, design and foundry groups. The role emphasizes debugging PV issues, implementing rule decks, and driving improvement through tooling benchmarks.

You will work with external vendors, perform impact analyses, and contribute to robust PV flows in a fast-paced embedded tech environment.