Senior RTL Design Engineer – Mixed-Signal IP (Hybrid)

Silicon Labs Careers; Hyderabad City Taluka; On-site; PKR 30,454,000 - 44,297,000; Full time

Benefits offered by this job

RSUs

Insurance plans with outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs is seeking an RTL Design Engineer for Mixed-Signal IPs to develop and verify digital RTL blocks within mixed-signal subsystems. You will work with analog/mixed-signal teams to ensure low-power, high-quality IP delivery for integration into complex SoCs.

You will design synthesizable RTL, participate in reviews, and drive test plans and coverage with verification teams, leveraging Cadence AMS/VCS AMS tools and scripting for automation.

Qualifications

• 3+ years of experience in digital RTL design with exposure to mixed-signal IP or subsystem development.
• Proficiency in Verilog/SystemVerilog and experience with synthesis and static verification flows (lint, CDC).
• Familiarity with analog/mixed-signal concepts such as signal sampling, clocking, calibration, and power management.
• Hands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS).
• Good understanding of digital communication protocols (SPI, I2C, APB, AXI).
• Exposure to scripting (Python, Perl, TCL) for automation and design flow enhancements.
• Experience working in cross-functional environments involving analog, verification, and SoC integration teams.

Responsibilities

• Develop synthesizable RTL for mixed-signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends.
• Collaborate with analog design engineers to define digital-analog interface specifications, control logic, and communication protocols.
• Ensure correct functionality and performance of mixed-signal IPs through behavioral modeling, simulation, and co-verification with analog components.
• Participate in design reviews, micro-architecture definition, and documentation of IP functionality and timing interfaces.
• Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses.
• Collaborate with verification engineers to define test plans, drive coverage closure, and debug issues across digital and analog boundaries.
• Integrate mixed-signal IPs into SoC top-level RTL and resolve functional or timing issues during full-chip validation.
• Contribute to continuous improvement of design methodologies, automation scripts, and reuse strategies for mixed-signal IP development.

Skills

Verilog/SystemVerilog

Synthesis & lint

Mixed-signal IP design

Python scripting

SPI/I2C/APB/AXI

Cross-functional collaboration

Debugging & verification

Education

B.E./B.Tech or M.S./M.Tech in Electrical Engineering

Tools

Cadence AMS Designer

Synopsys VCS AMS

Job description

Silicon Labs is seeking an RTL Design Engineer for Mixed-Signal IPs to develop and verify digital RTL blocks within mixed-signal subsystems. You will work with analog/mixed-signal teams to ensure low-power, high-quality IP delivery for integration into complex SoCs.

You will design synthesizable RTL, participate in reviews, and drive test plans and coverage with verification teams, leveraging Cadence AMS/VCS AMS tools and scripting for automation.