Senior CAD Digital Verification Engineer—Automation

Silicon Labs; Hyderabad City Taluka; On-site; PKR 24,889,000 - 35,951,000; Full time

Benefits offered by this job

Equity rewards (RSUs)

Employee Stock Purchase Plan (ESPP)

Insurance plans with Outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs is seeking a CAD Digital Verification Engineer to develop and support CAD tools and EDA flows for ASIC/SoC verification. You will automate testbench generation and verification workflows, collaborate with RTL teams, and work with Cadence, Synopsys, and Siemens EDA to optimize simulation efficiency.

You will contribute to low-power verification, formal verification, and coverage analysis, leveraging Python, Tcl, and C/C++ in a Linux environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.
• 7+ years of relevant industry experience or a Master's with 5+ years.
• Experience in Design Verification, CAD/EDA tool development, or verification flow support for ASIC/SoC designs.
• Strong programming and automation experience using Python, Perl, Tcl, C/C++, Makefiles, or shell scripting.

Responsibilities

• Develop, deploy, and maintain CAD tools and EDA flows supporting Design Verification, Formal Verification, Low Power, Functional Safety, and Coverage Analysis.
• Collaborate with RTL design and verification teams to understand requirements and improve productivity.
• Develop automation scripts to streamline simulation builds, testbench generation, and verification workflows.
• Support ASIC/SoC simulation environments, including RTL, GLS, and UVM-based verification flows.
• Collaborate with EDA vendors to integrate capabilities, debug tool issues, and resolve bottlenecks.
• Develop scalable CAD methodologies to improve verification quality and reduce turnaround time.

Skills

Python scripting

C/C++ programming

Verilog/SystemVerilog

UVM verification

Debugging

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Electronics, or Computer Engineering

Master's degree in Electrical/Computer Engineering (advantage)

Tools

Cadence tools

Synopsys tools

Siemens EDA

Job description

Silicon Labs is seeking a CAD Digital Verification Engineer to develop and support CAD tools and EDA flows for ASIC/SoC verification. You will automate testbench generation and verification workflows, collaborate with RTL teams, and work with Cadence, Synopsys, and Siemens EDA to optimize simulation efficiency.

You will contribute to low-power verification, formal verification, and coverage analysis, leveraging Python, Tcl, and C/C++ in a Linux environment.