Lead RTL Engineer — Mixed-Signal IPs & SoC Integration

Silicon Labs Careers; Hyderabad City Taluka; On-site; PKR 24,917,000 - 41,528,000; Full time

Benefits offered by this job

Equity Rewards (RSUs)

Insurance plans with Outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs in Hyderabad, Pakistan, seeks an RTL Design Engineer for Mixed-Signal IPs to develop, integrate, and verify digital RTL blocks within analog-digital subsystems for low-power SoCs. You will collaborate with analog designers, define digital-analog interfaces, run co-simulations, and contribute to IP quality through lint, CDC, and synthesis readiness.

You will work with system architects and SoC teams to enable seamless IP integration, participate in design reviews, and drive robust

Qualifications

• 5–10 years of experience in digital RTL design with mixed-signal IP exposure.
• Proficient in Verilog/SystemVerilog and synthesis flows (lint, CDC).
• Familiarity with analog/mixed-signal concepts such as signal sampling, clocking, and power management.
• Experience working across analog, verification, and SoC integration teams.

Responsibilities

• Develop synthesizable RTL for mixed-signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends.
• Collaborate with analog design engineers to define digital-analog interface specifications and control logic.
• Verify mixed-signal IPs through behavioral modeling, simulation, and co-verification with analog components.
• Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses.
• Integrate mixed-signal IPs into SoC top-level RTL and support full-chip validation.

Skills

Verilog/SystemVerilog

RTL design

Digital design principles

Co-simulation

Python scripting

Education

B.E./B.Tech in Electrical Engineering

M.S./M.Tech in Electronics or CE

Tools

Cadence AMS Designer

Synopsys VCS AMS

Job description

Silicon Labs in Hyderabad, Pakistan, seeks an RTL Design Engineer for Mixed-Signal IPs to develop, integrate, and verify digital RTL blocks within analog-digital subsystems for low-power SoCs. You will collaborate with analog designers, define digital-analog interfaces, run co-simulations, and contribute to IP quality through lint, CDC, and synthesis readiness.

You will work with system architects and SoC teams to enable seamless IP integration, participate in design reviews, and drive robust