Lead IC Verification Engineer – Modem Baseband & PHY

Silicon Labs Careers; Hyderabad City Taluka; On-site; PKR 33,241,000 - 49,861,000; Full time

Benefits offered by this job

Equity rewards (RSUs)

Insurance plans with outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs is seeking a Lead IC Verification Engineer to verify modem digital baseband and PHY-layer IPs for wireless SoCs. You will develop UVM environments, and drive coverage and constrained-random verification across teams.

You will collaborate with RTL designers, modem system engineers, and validation teams to ensure robust IP verification and timely delivery in a dynamic, tech-focused environment.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related field.
• 7–15 years of experience in RTL Design Verification, preferably involving mixed-signal datapath, modem baseband, or PHY-layer modules.
• Strong hands-on expertise in SystemVerilog and UVM verification methodologies.

Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments for modem digital baseband and PHY-layer IPs.
• Design and implement module-level and subsystem-level testbenches, including drivers, monitors, agents, scoreboards, and coverage models.
• Define and execute comprehensive verification plans to ensure functional correctness and design quality.
• Drive constrained-random verification, functional coverage, and coverage closure.
• Perform bit-exact verification by integrating C-based algorithmic reference models into verification environments.
• Verify complex mixed-signal datapath and PHY-layer modules used in wireless communication systems.
• Debug complex RTL and testbench issues, working closely with design and system engineering teams to identify root causes.
• Collaborate across functional teams to resolve integration challenges and ensure successful IP verification and delivery.
• Participate in design reviews, verification planning, and continuous improvement of verification methodologies.

Skills

SystemVerilog

UVM

Constrained-random testing

C-based reference models

RTL design verification

Debugging

Digital baseband

PHY-layer concepts

Education

Bachelor's or Master's in Electrical Engineering or related field

Tools

C-based reference models tooling

RTL debugging tools

Job description

Silicon Labs is seeking a Lead IC Verification Engineer to verify modem digital baseband and PHY-layer IPs for wireless SoCs. You will develop UVM environments, and drive coverage and constrained-random verification across teams.

You will collaborate with RTL designers, modem system engineers, and validation teams to ensure robust IP verification and timely delivery in a dynamic, tech-focused environment.