Senior Lead ASIC Verification Engineer - Network IP

JobCubby; Hinoba-an; On-site; PHP 5,629,000 - 8,130,000; Full time

Job summary

Qualcomm India Private Limited, a leading technology innovator, seeks a Hardware Engineer to plan, design, verify, and test electronic systems, including RTL/DFT, across multiple domains. You will collaborate globally to deliver world-class products.

The role emphasizes hands-on verification with Cadence/Synopsys tools, SV/UVM/C, and strong coding, documentation, and cross-functional teamwork. RF/analog knowledge and post-Si debugging are plus points.

Qualifications

• Bachelor's degree in Electronics/Engineering or related field with 3+ years Hardware Engineering experience.
• Master's or PhD with relevant experience is advantageous.
• Experience in RTL verification using SystemVerilog/UVM across multiple clock/power domains.

Responsibilities

• Verify digital front-end designs and testbenches with SV/UVM/C.
• Collaborate with Systems, SoC, SW, Validation & DFT teams to meet goals.
• Lead junior engineers and drive project planning and tracking.
• Develop verification strategy, testbench architecture and plans; implement tests.
• Perform HW verification using Cadence and Synopsys simulators; conduct regression and bug-triage.
• Engage in Formal Verification (Jasper, VCF) and power-aware verification.

Skills

ASIC verification

RTL design

SystemVerilog/UVM

Python/Perl scripting

Post-Si debugging

Documentation

Communication

Education

Bachelor's or higher in Electronics/Engineering

Master's or PhD preferred

Tools

Cadence tools

Synopsys tools

SV/UVM

Jasper/VCF (Formal Verification)

Job description

Qualcomm India Private Limited, a leading technology innovator, seeks a Hardware Engineer to plan, design, verify, and test electronic systems, including RTL/DFT, across multiple domains. You will collaborate globally to deliver world-class products.

The role emphasizes hands-on verification with Cadence/Synopsys tools, SV/UVM/C, and strong coding, documentation, and cross-functional teamwork. RF/analog knowledge and post-Si debugging are plus points.