Senior Digital Design Engineer RTL, DV & Mixed-Signal

Analog Devices, Inc.; Taguig; Hybrid; PHP 600,000 - 1,000,000; Full time

Job summary

Analog Devices, Inc. in the Philippines seeks a Digital Design Engineer to contribute to RTL design, subsystem implementation, and mixed‑signal integration under senior guidance.

You will work on digital verification aspects and learn to switch between design and DV roles as projects require. The role emphasizes developing skills in SystemVerilog, UVM, and scripting, while collaborating with DV, physical design, and analog teams to ensure proper timing and synthesis.

Qualifications

• BS or MS in ECE, EE, CpE, or equivalent.
• 2–5 years digital design experience, or strong NCG background.
• Proficiency in SystemVerilog/Verilog; familiarity with UVM preferred.
• Experience with scripting languages (Python/Perl/TCL).
• Basic understanding of AMS modeling and mixed-signal flows is a plus.
• Strong analytical, problemsolving, and communication skills.

Responsibilities

• Write RTL for digital blocks based on specifications.
• Perform lint, CDC analysis, and support DFT integration.
• Assist in writing functional testcases and simple UVM components.
• Collaborate with DV engineers for coverage closure and bug resolution.
• Support AMS co‑simulation and integration with analog blocks.
• Work with physical design teams on synthesis and timing.
• Train and develop skills in digital design verification.

Skills

SystemVerilog

RTL design

UVM

Python

CDC analysis

Education

BS in ECE/EE/CpE

Tools

UVM

Job description

Analog Devices, Inc. in the Philippines seeks a Digital Design Engineer to contribute to RTL design, subsystem implementation, and mixed‑signal integration under senior guidance.

You will work on digital verification aspects and learn to switch between design and DV roles as projects require. The role emphasizes developing skills in SystemVerilog, UVM, and scripting, while collaborating with DV, physical design, and analog teams to ensure proper timing and synthesis.