Junior Design Verification Engineer - SystemVerilog/UVM

Analog Devices, Inc.; Luan; On-site; PHP 4,411,000 - 6,301,000; Full time

Benefits offered by this job

Competitive compensation

Comprehensive benefits

Work-life balance

Job summary

Analog Devices, Inc. is seeking an Associate Design Verification Engineer to develop and verify digital, analog, and mixed-signal products before tape-out.

This entry-level role emphasizes learning under close supervision, with hands-on experience in verification methodologies and collaboration with senior engineers who will mentor your growth. You will gain exposure to test benches, SystemVerilog/UVM environments, and code coverage while supporting verification planning and documentation across

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, or related field.

Responsibilities

• Develop and execute basic test benches for mixed-signal product verification.
• Create and maintain basic test environments using SystemVerilog/UVM.
• Conduct code coverage analysis to ensure design accuracy.
• Debug simulation failures and track coverage metrics.
• Support verification planning and documentation.
• Collaborate with design teams to understand requirements.
• Identify potential design issues under guidance of senior team members.
• Document verification processes and results.

Skills

SystemVerilog/UVM

Scripting (Python/Perl/TCL)

Verilog RTL

Digital Interfaces (I2C/SPI/UART)

Simulation Tools

Problem Solving

Communication

Education

Bachelor's degree in Electrical Engineering / Electronics & Communications / Computer Engineering or related field

Job description

Analog Devices, Inc. is seeking an Associate Design Verification Engineer to develop and verify digital, analog, and mixed-signal products before tape-out.

This entry-level role emphasizes learning under close supervision, with hands-on experience in verification methodologies and collaboration with senior engineers who will mentor your growth. You will gain exposure to test benches, SystemVerilog/UVM environments, and code coverage while supporting verification planning and documentation across