IC TEST ENGINEER

As PowerUp; Metro Manila; On-site; PHP 600,000 - 1,200,000; Full time

Job summary

As PowerUp in Metro Manila is seeking a seasoned Test Engineer to develop production test programs for ATE systems and translate test specifications from ATPG patterns and memory BIST into executable plans.

You will characterize silicon across PVT corners, optimize test time, and drive yield analysis with RTL/PD/DFT teams to reduce cost of test. The role is on-site in Manila, Philippines.

Qualifications

• Experience developing production test programs for ATE systems.
• Ability to translate test specs from ATPG patterns and memory BIST.
• Experience characterizing silicon across PVT corners.
• Skilled in optimizing test time and reducing cost of test.
• Experience with yield analysis and RCA with RTL/PD/DFT teams.

Responsibilities

• Develop production test programs on ATE for functional, parametric, and structural test.
• Define test specifications from ATPG patterns and memory BIST to executable test plans.
• Characterize silicon across PVT corners including Iddq, dynamic current, speed bins, and analog parametrics.
• Optimize test time via parallel testing, step reordering, and adaptive test strategies.
• Drive yield analysis with Pareto dashboards and RCA collaboration with RTL/PD/DFT teams.

Skills

Test program development

ATE testing

ATPG patterns

Memory BIST

Yield analysis

Troubleshooting hardware/test

Tools

Advantest V93000

Teradyne UltraFLEX

DFT tooling

Job description

Job Description:

• Develop production test programs on ATE (Advantest V93000, Teradyne UltraFLEX, or equivalent) for functional, parametric, and structural test.
• Define test specification from ATPG patterns, memory BIST, and functional test cases; translate to ATE-executable test plans.
• Characterize silicon across PVT corners during NPI: Iddq, dynamic current, speed bins, and analog parametrics (ADC, PLL jitter).
• Optimize test time: parallel test strategy, step reordering, and adaptive test to minimize cost-of-test.
• Drive yield analysis: Pareto dashboards, failure mode ID, RCA with RTL/PD/DFT teams.

Requirements: