Top level AMS verification engineer

USG Engineering; Eindhoven; Vor Ort; EUR 60.000 - 80.000; Vollzeit

Zusammenfassung

USG Engineering in Nijmegen is seeking a top-level analog mixed-signal verification engineer to develop ASICs for automotive magnetic sensors. The successful candidate will have over 5 years of experience in verification using netlists and Verilog-AMS models, and must be fluent in English and Dutch.

This role offers the opportunity to work in a multi-discipline environment, contributing to the success of innovative automotive solutions.

Qualifikationen

• 5+ years experience in high-level digital description languages.
• 5+ years experience in Linux/Unix and C/C++/SystemC/System-Verilog programming.
• 5+ years experience in scripting languages for self-checking test benches.

Aufgaben

• Development of ASICs for magnetic sensor products.
• Verification of functional requirements using a mix of netlists and Verilog-AMS models.
• Ability to adopt or improve existing solutions in a multi-discipline environment.

Kenntnisse

Top-level analog mixed-signal verification

Digital design background

Verification using netlists and Verilog-AMS models

High-level digital description languages (Verilog, VHDL)

Linux/Unix and C/C++/SystemC/System-Verilog programming

Scripting languages (TCL, Perl)

Cadence and Spectre design tools

Verilog-AMS modelling

Fluent in English and Dutch

Ausbildung

MSc degree in Electrical Engineering

Tools

Cadence

Spectre

Jobbeschreibung

Job Description

The project develops a High End magnetic Speed Sensor for Automotive ABS applications. First engineering samples are available and the project prepares for the redesign being the final product. 100% verification coverage is the target to be met before the tape‑out.

Qualifications

• Top‑level analog mixed‑signal verification engineer with a digital design background, responsible for the development of ASICs for magnetic sensor products in Nijmegen.
• Verification of all functional requirements of the new product at top level using a mix of netlists and Verilog‑AMS models for analog modules combined with the digital module in RTL code.
• 5+ years experience in high‑level digital description languages (Verilog, VHDL, …).
• 5+ years experience in Linux/Unix and C/C++/SystemC/System‑Verilog programming.
• 5+ years experience in scripting languages (TCL and/or Perl) for self‑checking test benches.
• 5+ years experience in Cadence and Spectre design tools.
• 5+ years experience in Verilog‑AMS modelling of analog modules.
• Sector know‑how in digital IC design and analog mixed‑signal verification.
• Fluent in English (speaking and writing); project language English and Dutch.
• Must have experience in top‑level AMS verification with self‑checking test benches.
• MSc degree in Electrical Engineering.
• Hands‑on experience with Cadence and Spectre tools.
• Ability to adopt or improve existing solutions, work independently, and as a team player in a multi‑discipline, multi‑site environment.
• Seniority: 5–10 years (Medior).

Your employment contract will be concluded with USG Engineering or one of our partner companies, and USG Engineering will take care of work and resident permits.