Senior Analog Layout Engineer - 22nm SERDES & PLLs

Chipright Inc.; Netherlands; On-site; EUR 70,000 - 100,000; Full time

Job summary

Chipright Inc. in the Netherlands is seeking a seasoned Analog Layout Engineer to join a team of experienced engineers working on 22nm deep micron CMOS technology. The role requires strong hands-on experience in high-speed layout and layout of critical blocks such as PLLs and transceivers.

You will work with advanced EDA tools (Synopsys, Cadence) and collaborate on floor planning, power routing, DRC, and physical verification to ensure feasible, repeatable layouts and robust designs.

Qualifications

• 5+ years of Analog Layout experience.
• High-speed SERDES layout experience.
• Layout of PLLs, transceivers, receivers.
• Experience on deep sub-micron CMOS (28nm or below).
• Proficient with Synopsys & Cadence tools.
• Ability to influence architecture-level design for layout feasibility.
• Experience with floorplanning, power routing and ESD design.
• Experience with Place & Route and layout finishing.
• Experience with DRC and physical verification.
• Experience working with EDA tool vendors to maximize tool output.
• Strong debugging and problem-solving skills.

Skills

Analog Layout

High Speed Layout

Block/Layout blocks (PLLs, Transceiv.,

Deep sub-micron CMOS (28nm or less)

Architecture influence on layout

Floor Planning & Power Routing

Place & Route/Layout finishing

DRC & Physical Verification

EDAs tool optimization

Problem solving

Education

Engineering degree

Tools

Synopsys

Cadence

Job description

Chipright Inc. in the Netherlands is seeking a seasoned Analog Layout Engineer to join a team of experienced engineers working on 22nm deep micron CMOS technology. The role requires strong hands-on experience in high-speed layout and layout of critical blocks such as PLLs and transceivers.

You will work with advanced EDA tools (Synopsys, Cadence) and collaborate on floor planning, power routing, DRC, and physical verification to ensure feasible, repeatable layouts and robust designs.