Lead Digital ASIC Verification Engineer – SoC Innovation

Visa Hunt; Delft; Remote; EUR 90,000 - 120,000; Full time

Job summary

Qualinx is seeking a Digital ASIC Verification Engineer to verify digital IP blocks and perform post-layout verification within upcoming SoCs. You will develop test benches and ensure RTL implementations meet timing and functional requirements.

You will collaborate with backend teams to address synthesis constraints, timing closure, and ECOs, while contributing to Lint and CDC checks to guarantee design integrity across the verification flow.

Qualifications

• Experience with SystemVerilog and UVM for ASIC verification.
• Develop test benches and verify digital IP blocks.
• Coordinate with backend teams on synthesis, timing and ECO.

Responsibilities

• Verify digital IP blocks and chip-level post-layout verification.
• Develop test benches for block-level functional verification.
• Collaborate with backend/implementation teams to address synthesis, timing, and ECO issues.

Skills

SystemVerilog

UVM

ASIC Verification

RTL Design

Test Benches

Post-layout Verification

Synthesis

DFT

Lint

CDC

ECO

Job description

Qualinx is seeking a Digital ASIC Verification Engineer to verify digital IP blocks and perform post-layout verification within upcoming SoCs. You will develop test benches and ensure RTL implementations meet timing and functional requirements.

You will collaborate with backend teams to address synthesis constraints, timing closure, and ECOs, while contributing to Lint and CDC checks to guarantee design integrity across the verification flow.