Senior SoC Architect - Low-Power GNSS/IoT SoC

Qualinx BV; Delft; Sur place; EUR 120 000 - 180 000; Plein temps

Résumé du poste

Qualinx, a cutting-edge start-up born from TU Delft, seeks a senior SoC Architect to define the high-level architecture of our groundbreaking GNSS/Digital RF SoC. You will shape the chip’s components, guide hardware teams, and collaborate with firmware to ensure efficient software execution across drivers and operating systems.

The role demands deep expertise in RTL design, verification, ARM subsystems, memory architectures, and IP integration.

Qualifications

• Minimum 12 years in RTL Design and verification, CPU-based chip concepts.
• Deep understanding of ARM MCU subsystems, memory controllers, and memory architectures.
• 10+ years in Digital ASIC Flows, RTL design, verification, debug and test methodologies.
• Solid chip packaging understanding and hardware-software interface design experience.
• Experience with IP integration, interconnects, and IP management tasks.

Responsabilités

• Define high-level SoC architecture and component inclusion.
• Guide chip physical design with hardware teams.
• Coordinate with firmware/GNSS for software support and drivers.
• Define and implement security features for the SoC.
• Ensure scalable, adaptable architecture for future generations.
• Manage timelines, deliverables, and budget for SoC development.

Connaissances

RTL Design

RTL Verification

CPU Architecture

ARM MCUs

Memory Architectures

Digital ASIC Flows

DFT/JTAG/Scan

IP Integration

Signal Integrity

Power/Low Power

Clock/Reset Architecture

Outils

AMBA/AXI/AHB

PLL/DAC/ADC/LNA

IP Selection

Description du poste

Qualinx, a cutting-edge start-up born from TU Delft, seeks a senior SoC Architect to define the high-level architecture of our groundbreaking GNSS/Digital RF SoC. You will shape the chip’s components, guide hardware teams, and collaborate with firmware to ensure efficient software execution across drivers and operating systems.

The role demands deep expertise in RTL design, verification, ARM subsystems, memory architectures, and IP integration.