SoC Architect

Qualinx BV; Delft; On-site; EUR 120,000 - 180,000; Full time

Job summary

Qualinx, a cutting-edge start-up born from TU Delft, seeks a senior SoC Architect to define the high-level architecture of our groundbreaking GNSS/Digital RF SoC. You will shape the chip’s components, guide hardware teams, and collaborate with firmware to ensure efficient software execution across drivers and operating systems.

The role demands deep expertise in RTL design, verification, ARM subsystems, memory architectures, and IP integration.

Qualifications

• Minimum 12 years in RTL Design and verification, CPU-based chip concepts.
• Deep understanding of ARM MCU subsystems, memory controllers, and memory architectures.
• 10+ years in Digital ASIC Flows, RTL design, verification, debug and test methodologies.
• Solid chip packaging understanding and hardware-software interface design experience.
• Experience with IP integration, interconnects, and IP management tasks.

Responsibilities

• Define high-level SoC architecture and component inclusion.
• Guide chip physical design with hardware teams.
• Coordinate with firmware/GNSS for software support and drivers.
• Define and implement security features for the SoC.
• Ensure scalable, adaptable architecture for future generations.
• Manage timelines, deliverables, and budget for SoC development.

Skills

RTL Design

RTL Verification

CPU Architecture

ARM MCUs

Memory Architectures

Digital ASIC Flows

DFT/JTAG/Scan

IP Integration

Signal Integrity

Power/Low Power

Clock/Reset Architecture

Tools

AMBA/AXI/AHB

PLL/DAC/ADC/LNA

IP Selection

Job description

Join our cutting-edge start-up adventure! Who are we? Join the Revolution in GNSS and IoT Connectivity At Qualinx , we're not just building chips, we're engineering the future fabric of the connected world. As a pioneering semiconductor scale-up, we're transforming how devices connect, communicate, and operate through our ground-breaking Digital RF technology. Our mission goes beyond ultra-low power GNSS: we're redefining what's possible in adaptive, scalable, and intelligent connectivity for the Internet of Things. Born from deep-tech innovation at TU Delft, our team of visionary engineers and bold thinkers is tackling the toughest challenges in GNSS and IoT, starting with power consumption and expanding into dynamic, context-aware solutions that adapt to any environment or use case. We've already achieved what many thought impossible: the world's most advanced GNSS chipset. But that's just the beginning. At Qualinx, we believe that the future of connectivity lies in precision, efficiency, and adaptability. Our ambition is to become the invisible thread that seamlessly interconnects billions of devices: powering a smarter, more responsive world.

What Sets Us Apart

Joining Qualinx is about becoming part of a culture that’s as ambitious as it is authentic. We hold ourselves to high standards, thrive on solving the unexpected, and push boundaries together. But we also know how to enjoy the ride. Our culture is a unique blend of curiosity, team spirit, and a touch of unconventional charm. It's fast-paced, fun, and grounded in a sober sense of purpose and perspective. Whether we're deep in design reviews or sharing laughs over lunch, we're building something meaningful together. At Qualinx, you're not just contributing to a ground-breaking technology, you're helping shape a team that's redefining what it means to work in deep tech.

Job Description

Key Responsibilities

• System Design & Integration: You will be responsible for defining the high-level architecture of the SoC, determining which components will be included on the chip.
• You will collaborate with the hardware design teams to guide the implementation of the chip's physical design.
• You will coordinate with our firmware & GNSS team to ensure the SoC Architecture supports efficient execution of software, including drivers, operating systems and applications.
• You will define and implement security features to protect the SoC from vulnerabilities.
• You will keep up with the advances in the semiconductor industry and make sure the SoC architecture remains scalable and adaptable for future generations of products.
• Managing product timelines and deliverables, making sure that the SoC Development follows the planned schedule and stays within budget.

Requirements

• Qualinx is looking for a result-driven and conscientious senior SoC Architect. Someone who thrives in an environment where your proactive and can-do attitude is highly appreciated. The ideal candidate for this role must have: Minimum of 12 years experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.
• Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe...).
• At least 10 years' experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).
• Solid understanding of chip packaging.
• Proficient in hardware-software interface design, including device drivers, firmware, and low-level software optimizations.
• Strong problem-solving skills to troubleshoot and resolve architectural issues related to SoC integration, performance, and power efficiency.
• Experienced with silicon bring-up, validation, and post-silicon debug methodologies.
• Practical experience with IP integration, including integration flows, interconnect design (e.g., AMBA, AXI, AHB), and managing key IP integration architecture tasks.
• Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).
• Experience in analog-digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO... integration, and layout constraints for minimizing noise and signal interference.
• Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).
• Deep understanding of library selection and design, with a focus on leakage power-aware methodologies to optimize performance and power trade-offs.
• Hands-on experience with IP selection to meet the specific needs of the design.
• Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.
• Strong knowledge of pad ring placement and ESD strategy.
• In-depth expertise in clock and reset architecture design, including low-jit