Senior Physical Design Engineer

IC Resources; Zuid-Holland; On-site; EUR 85,000 - 120,000; Full time

Benefits offered by this job

Stocks

Bonus

Visa sponsorship

Job summary

IC Resources is seeking a Senior Physical Design Engineer for a major US semiconductor manufacturer. You will help establish and expand an in-house ASIC implementation team, developing precision timing and mixed-signal products, and contribute to RTL-to-GDSII flows.

Join a global engineering organization to build physical design methodologies from scratch, collaborate with RTL, analog, verification, and product teams, and drive tape-out cycles to deliver silicon on schedule.

Qualifications

• Degree / Masters / Doctorate in Electronics, Microelectronics, Physics, Computer Engineering, or a related field.
• Experience building Cadence-based physical design flows and methodologies from scratch is essential.
• Strong industry experience delivering complex ASICs through successful tape-out.
• Proven expertise across the full RTL-to-GDSII implementation flow.

Responsibilities

• Build and maintain Cadence-based physical design flows and methodologies from scratch.
• Deliver complex ASICs through successful tape-out, collaborating with frontend, verification, and analog teams.

Skills

Cadence-based PD flows

ASIC tape-out experience

RTL-to-GDSII flow

Floorplanning & PnR

CTS & clock tree synthesis

STA & timing closure

Power/Signal integrity

Scripting (Tcl, Python, Perl, Shell)

Cross-functional collaboration

Education

Electronics / Microelectronics / Physics / CE (Degree/Master/PhD)

Tools

Cadence

GDSII tooling

UPF

EM/IR analysis tooling

Python/Tcl scripting

Job description

A major US semiconductor manufacturer is looking for a Senior Physical Design Engineer to help establish and expand its in‑house ASIC implementation team, supporting the development of cutting‑edge precision timing and mixed‑signal semiconductor products. You will join a highly successful global engineering organization responsible for the implementation and delivery of complex digital and mixed‑signal ASICs. This is a unique opportunity to play a key role in building physical design methodologies and flows from the ground up, working closely with RTL, analog, verification, and product engineering teams across the full RTL‑to‑GDSII flow.

Responsibilities

Build and maintain Cadence‑based physical design flows and methodologies from scratch, deliver complex ASICs through successful tape‑out, and collaborate closely with front‑end, verification, and analog teams to achieve successful silicon delivery.

Qualities & Requirements

• Degree / Masters / Doctorate in Electronics, Microelectronics, Physics, Computer Engineering, or a related field.
• Experience building Cadence‑based physical design flows and methodologies from scratch is essential.
• Strong industry experience delivering complex ASICs through successful tape‑out.
• Proven expertise across the full RTL‑to‑GDSII implementation flow.
• Floorplanning, power planning, power grid design, place and route (PnR), clock tree synthesis (CTS), and physical verification.
• Advanced Static Timing Analysis (STA), timing closure, timing constraints, and ECO implementation.
• Experience with low‑power implementation methodologies and UPF.
• Strong understanding of signal integrity, power integrity, EM/IR analysis, and physical sign‑off.
• Scripting and automation skills using Tcl, Python, Perl, or Shell scripting.
• Ability to work closely with front‑end, verification, and analog teams to achieve successful silicon delivery.

Excellent salaries, benefits, stocks, bonus, and visa sponsorship are available for the correctly qualified candidate.