Senior FPGA Engineer: High-Performance Networking

Fortaegis Technologies; Amsterdam; On-site; EUR 90,000 - 120,000; Full time

Job summary

Fortaegis Technologies in Amsterdam seeks an experienced FPGA Engineer to design and implement FPGA solutions for networking and security products. You will translate system requirements into high‑performance FPGA designs and collaborate with hardware and software teams to ensure seamless integration.

The role emphasizes rigorous timing analysis, hands‑on lab validation, and the chance to influence next‑gen SoC architecture.

Qualifications

• Must have 5+ years FPGA design and implementation experience.
• Hands-on experience with Xilinx FPGAs (Vivado, Vitis) required.
• Strong digital design, timing, and high-speed interfaces knowledge.
• Experience with hardware/software integration in networking or security systems.
• Lab testing, debugging, and validation of FPGA designs.

Responsibilities

• Design and implement FPGA logic based on system-level requirements.
• Develop and maintain block diagrams, constraints, and pin mappings.
• Enable and integrate multiple interfaces (e.g., networking, memory, PCIe, high-speed SerDes).
• Implement and verify FPGA functionality using VHDL/Verilog or SystemVerilog.
• Test, validate, and debug FPGA designs in lab and simulation environments.
• Collaborate with hardware and software teams to ensure seamless system integration.
• Perform timing analysis, optimization, and resource management for high-performance designs.
• Contribute to design reviews and provide recommendations for FPGA architecture improvements.

Skills

Digital design

FPGA implementation

Requirements translation

Cross-functional teamwork

Independent work

Tools

Vivado

Vitis

Verilog

VHDL

SystemVerilog

Job description

Fortaegis Technologies in Amsterdam seeks an experienced FPGA Engineer to design and implement FPGA solutions for networking and security products. You will translate system requirements into high‑performance FPGA designs and collaborate with hardware and software teams to ensure seamless integration.

The role emphasizes rigorous timing analysis, hands‑on lab validation, and the chance to influence next‑gen SoC architecture.