Design Verification Engineer

Fortaegis Technologies; Amsterdam; On-site; EUR 90,000 - 120,000; Full time

Job summary

Fortaegis is seeking a Design Verification Engineer in Amsterdam to verify RTL designs for FPGA and ASIC-based products. You will develop verification strategies, maintain environments, and collaborate with design and software teams to ensure correct functionality and performance.

The role emphasizes ownership, problem-solving, and staying current with verification tools and best practices in a fast-growing semiconductor company.

Qualifications

• 5+ years of RTL verification experience for FPGA and/or ASIC designs
• Advanced knowledge of SystemVerilog and UVM
• Hands-on experience with verification EDA tools (Siemens, Cadence, Synopsys)
• Strong analytical and problem-solving abilities with keen attention to detail
• Experience with formal verification techniques is a plus
• High-speed networking (Ethernet, PCIe) or cryptographic IP experience is advantageous
• Effective communication and teamwork across functions
• Ownership mindset and solution-oriented approach

Responsibilities

• Develop and execute verification strategies for intricate FPGA and ASIC RTL designs
• Design, implement, and maintain verification environments including automated test suites and infrastructure
• Identify, debug and document design issues, collaborating with design engineers to validate functionality
• Implement coverage-focused verification approaches to ensure thorough verification of all features
• Coordinate with design, architecture, and software teams to ensure smooth integration and verification
• Stay up-to-date with verification tools, methodologies and best practices

Job description

Fortaegis is a fast-scaling, highly ambitious and cutting-edge semiconductor company. We are looking for a Design Verification Engineer responsible for verifying RTL designs for FPGA and ASIC-based products. The role focuses on ensuring that system-level and block-level requirements are correctly implemented in hardware designs and identifying functional issues early. We are looking for candidates with not only an exceptional skillset, but also an exceptional mindset, willing to go above and beyond to make our hardware engineering teameven better.

Job requirements:

• 5+ years of experience in RTL functional verification for FPGA and/or ASIC designs
• Advanced knowledge of SystemVerilog and UVM
• Hands-on experience with verification EDA tools (e.g., Siemens, Cadence, Synopsys)
• Strong analytical and problem-solving abilities with keen attention to detail
• Experience with formal verification techniques is a plus
• High-speed networking (Ethernet, PCIe) or cryptographic IP experience is advantageous
• Effective communication, teamwork skills and ability to collaborate across functions
• Ability to take ownership and solve problems beyond the scope of the job description, with a flexible, solution-oriented mindset

Job responsibilities:

• Develop and execute verification strategies for intricate FPGA and ASIC RTL designs
• Design, implement, and maintain verification environments, including automated test suites and infrastructure, following industry-standard methodologies
• Identify, debug, and document design issues, collaborating closely with design engineers to validate functionality and performance
• Implement coverage-focused verification approaches to achieve thorough verification of all design features
• Coordinate with design, architecture, and software teams to ensure smooth integration and verification of designs
• Stay up-to-date with verification tools, methodologies, and best practices

Additional information:

The successful candidate will have the unique opportunity to participate in shaping the future of our visionary company, contributing to the development of ultra-secure and high-performance products. They will be part of a dynamic and innovative team, working in a collaborative and technically rewarding environment at the forefront of semiconductor technology.