System Validation Engineer

UST Malaysia; Seberang Perai; On-site; MYR 60,000 - 90,000; Full time

Job summary

UST Malaysia is seeking a dynamic Systems Validation Engineer to contribute to post-silicon validation, define test strategies, and help debug failures across architecture, design, and pre-silicon integration teams.

In this high-visibility role you will deliver system validation tests, improve automation, and collaborate with global teams to ensure silicon quality for our product family.

Qualifications

• 3+ years’ experience of validation and debugging in related industry.
• B.Sc. or Master’s in Electrical/Computer Engineering.
• Self-motivated and able to work independently and effectively to meet time.

Responsibilities

• Define test strategy for post-silicon validation and issue debugging.
• Collaborate with function teams and drive the work end to end from planning to execution.
• Deliver professional project reports to management, highlighting risk with solutions.
• Make improvements to system-level integration/test strategies, methodologies, and processes.
• Collaborate with multi-functional hardware and software teams to debug and tackle complex issues.
• Develop and improve automation features according to requirements.

Skills

System validation

Automation development

Python scripting

Cross-functional teamwork

Education

B.Sc. or M.S. in Electrical/Computer Engineering

Tools

Windows

Linux

Job description

We are looking for a dynamic, energetic Systems Validation Engineer to join our growing team. To work on the development of methodologies, the execution of system integration/System plans, and debugging of failures. As a key contributor you will collaborate with Architecture, Design, and Pre-silicon integration teams to improve post-silicon test content and provide feedback for future debug and test features. You will use and apply platform level tools and techniques to ensure Silicon quality.

The Person:

As a Systems Validation Engineer, you will deliver our next generation of system validation tests for our products. In this high visibility position, your systems engineering expertise will be necessary to find and resolve silicon platform issues.

KEY RESPONSIBILITIES:

• Work with global teams closely to define test strategy, work out smart system validation plan on post silicon level and fast response on issue debug.
• Collaborate with function teams and drive the work end to end from planning, execution, issue debug.
• Deliver professional project report to management, highlight risk in time with solution plans.
• Make improvements to system level integration/System level test strategies, methodologies, and processes.
• Collaboration with multi-functional hardware and software teams to debug and tackle complex issues.
• Develop and improve automation features according to requirements.

PREFERRED EXPERIENCE:

• Strong PC technology background and familiar with x86 system, APU/CPU/GPU products, system features, power management, etc.
• Strong technical knowledge for variant type of System Level Validation (Unit level, Integrity Level and System Level)
• Excellent communication skills, demonstrated success in working across geographies and cross functional teams
• Familiar with Windows and Linux environment.
• Script or coding (Python, C, Perl, Ruby) capability is a strong plus, automation and validation farm experience is a strong plus.

ACADEMIC CREDENTIALS:

• A B.Sc. Or Master’s Degree in Electrical/Computer Engineering.
• 3+ years’ experience of validation, debug in related industry.
• Self-motivated and able to work independently and effectively to meet time.