System Validation Engineer - Post-Silicon Debug & Automation

UST Malaysia; Seberang Perai; On-site; MYR 60,000 - 90,000; Full time

Job summary

UST Malaysia is seeking a dynamic Systems Validation Engineer to contribute to post-silicon validation, define test strategies, and help debug failures across architecture, design, and pre-silicon integration teams.

In this high-visibility role you will deliver system validation tests, improve automation, and collaborate with global teams to ensure silicon quality for our product family.

Qualifications

• 3+ years’ experience of validation and debugging in related industry.
• B.Sc. or Master’s in Electrical/Computer Engineering.
• Self-motivated and able to work independently and effectively to meet time.

Responsibilities

• Define test strategy for post-silicon validation and issue debugging.
• Collaborate with function teams and drive the work end to end from planning to execution.
• Deliver professional project reports to management, highlighting risk with solutions.
• Make improvements to system-level integration/test strategies, methodologies, and processes.
• Collaborate with multi-functional hardware and software teams to debug and tackle complex issues.
• Develop and improve automation features according to requirements.

Skills

System validation

Automation development

Python scripting

Cross-functional teamwork

Education

B.Sc. or M.S. in Electrical/Computer Engineering

Tools

Windows

Linux

Job description

UST Malaysia is seeking a dynamic Systems Validation Engineer to contribute to post-silicon validation, define test strategies, and help debug failures across architecture, design, and pre-silicon integration teams.

In this high-visibility role you will deliver system validation tests, improve automation, and collaborate with global teams to ensure silicon quality for our product family.