System Validation Engineer

UST Malaysia; Penang; On-site; MYR 60,000 - 100,000; Full time

Job summary

UST Malaysia is seeking a Systems Validation Engineer to drive post‑silicon validation strategies and hands‑on debug across architecture, design and pre‑silicon integration teams.

The role emphasizes enhancing system‑level validation content, cross‑functional collaboration, and automation development for robust silicon quality. Candidates should have 3+ years of validation experience and a strong electronics background.

Qualifications

• B.Sc. or Master’s Degree in Electrical/Computer Engineering required.
• 3+ years’ experience in validation and debugging in related industry.
• Self-motivated and able to work independently to meet time constraints.

Responsibilities

• Define test strategy with global teams for post‑silicon validation.
• Lead end‑to‑end validation from planning to issue debug.
• Deliver project reports highlighting risks with mitigation plans.
• Improve system‑level integration/test strategies, methodologies and processes.
• Collaborate with hardware and software teams to debug complex issues.
• Develop and enhance automation features per requirements.

Skills

System validation

x86 platforms

Windows & Linux

Scripting: Python/C/Perl/Ruby

Cross-functional collaboration

Automation

Education

B.Sc. or Master’s Degree in Electrical/Computer Engineering

Job description

THE ROLE: We are looking for a dynamic, energetic Systems Validation Engineer to join our growing team. To work on the development of methodologies, the execution of system integration/System plans, and debugging of failures. As a key contributor you will collaborate with Architecture, Design, and Pre‑silicon integration teams to improve post‑silicon test content and provide feedback for future debug and test features. You will use and apply platform level tools and techniques to ensure Silicon quality.

The Person: As a Systems Validation Engineer, you will deliver our next generation of system validation tests for our products. In this high visibility position, your systems engineering expertise will be necessary to find and resolve silicon platform issues.

KEY RESPONSIBILITIES

• Work with global teams closely to define test strategy, work out smart system validation plan on post‑silicon level and fast response on issue debug.
• Collaborate with function teams and drive the work end to end from planning, execution, issue debug.
• Deliver professional project report to management, highlight risk in time with solution plans.
• Make improvements to system level integration/System level test strategies, methodologies, and processes.
• Collaboration with multi‑functional hardware and software teams to debug and tackle complex issues.
• Develop and improve automation features according to requirements.

PREFERRED EXPERIENCE

• Strong PC technology background and familiar with x86 system, APU/CPU/GPU products, system features, power management, etc.
• Strong technical knowledge for variant type of System Level Validation (Unit level, Integrity Level and System Level).
• Excellent communication skills, demonstrated success in working across geographies and cross‑functional teams.
• Familiar with Windows and Linux environment.
• Script or coding (Python, C, Perl, Ruby) capability is a strong plus, automation and validation farm experience is a strong plus.

ACADEMIC CREDENTIALS

• A B.Sc. or Master’s Degree in Electrical/Computer Engineering.
• 3+ years’ experience of validation, debug in related industry.
• Self‑motivated and able to work independently and effectively to meet time.