Post-Silicon System Validation Engineer

UST Malaysia; Penang; On-site; MYR 60,000 - 100,000; Full time

Job summary

UST Malaysia is seeking a Systems Validation Engineer to drive post‑silicon validation strategies and hands‑on debug across architecture, design and pre‑silicon integration teams.

The role emphasizes enhancing system‑level validation content, cross‑functional collaboration, and automation development for robust silicon quality. Candidates should have 3+ years of validation experience and a strong electronics background.

Qualifications

• B.Sc. or Master’s Degree in Electrical/Computer Engineering required.
• 3+ years’ experience in validation and debugging in related industry.
• Self-motivated and able to work independently to meet time constraints.

Responsibilities

• Define test strategy with global teams for post‑silicon validation.
• Lead end‑to‑end validation from planning to issue debug.
• Deliver project reports highlighting risks with mitigation plans.
• Improve system‑level integration/test strategies, methodologies and processes.
• Collaborate with hardware and software teams to debug complex issues.
• Develop and enhance automation features per requirements.

Skills

System validation

x86 platforms

Windows & Linux

Scripting: Python/C/Perl/Ruby

Cross-functional collaboration

Automation

Education

B.Sc. or Master’s Degree in Electrical/Computer Engineering

Job description

UST Malaysia is seeking a Systems Validation Engineer to drive post‑silicon validation strategies and hands‑on debug across architecture, design and pre‑silicon integration teams.

The role emphasizes enhancing system‑level validation content, cross‑functional collaboration, and automation development for robust silicon quality. Candidates should have 3+ years of validation experience and a strong electronics background.