Signal Integrity Engineer

UST Malaysia; Penang; On-site; MYR 120,000 - 190,000; Full time

Job summary

UST Malaysia is seeking an experienced engineer to perform system-level PI analysis and develop PDN models for package- and board-level power delivery networks. You will conduct DC, AC, and transient simulations using PowerSI, PowerDC, ADS, and HSPICE.

You will also perform SI analysis for high-speed interfaces across package, PCB and connector interconnects, using HFSS for model extraction and ADS for end-to-end channel analysis; familiarity with IBIS-AMI modeling, jitter analysis, and

Qualifications

• 5–10 years of experience in SI/PI field.
• Proven familiarity with high-speed interfaces and modeling.
• Experience with PCB/ package layouts review.

Responsibilities

• Perform system-level PI analysis and develop PDN models.
• Conduct DC, AC, and transient simulations using listed tools.
• Carry out SI analysis for DDR/PCIe/USB/SerDes across interconnects.

Skills

PI analysis

SI analysis

Signal integrity

Channel analysis

Tools

PowerSI

PowerDC

ADS

HSPICE

HFSS

Cadence Allegro

Job description

Job description:

Perform system-level power integrity (PI) analysis, including extraction and development of package- and board-level PDN models and construction of system-level power delivery networks; conduct DC, AC, and transient simulations using PowerSI, PowerDC, ADS, and HSPICE.

Perform signal integrity (SI) analysis for high-speed interfaces (e.g., DDR/LPDDR, PCIe, USB, SerDes, Ethernet) across package, PCB, and connector interconnects, using HFSS for model extraction and ADS for end-to-end channel analysis; working knowledge of IBIS-AMI modeling, jitter analysis, and equalization techniques (e.g., CTLE, DFE, FFE) preferred.

Review package and PCB layouts in Cadence Allegro.

Working experience : 5- 10 years in SI/PI field