Senior/Staff Design Verification Engineer

Bitdeer (NASDAQ: BTDR); Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Bitdeer seeks a Design Verification Engineer to join its IC development team in Penang. You will develop verification environments and test plans to ensure correctness and performance of computer arithmetic IPs, collaborating with design and verification teams to deliver high‑quality silicon.

You will apply UVM, SystemVerilog, Verilog, and SVA in verification tasks, and use advanced tools like Palladium, HAPS, and Zebu for coverage-driven verification and regression.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (or currently pursuing).
• Solid understanding of digital logic design and RTL development using Verilog or other HDL.
• Proficiency with AMBA bus protocols (AXI, AHB, APB).
• Hands‑on experience with RTL simulation, debugging, and waveform analysis using EDA tools (Synopsys, Cadence, or Siemens EDA / Mentor).
• Proficiency with SystemVerilog and modern verification methodologies such as UVM.
• Proficiency with formal verification tools (VC Formal or JasperGold) and main applications (FPV, DPV, etc).
• Familiarity with Linux/Unix environments and scripting for automation (e.g., Bash, C Shell, Perl, or Python).
• Experience using version control systems such as Git or SVN in a collaborative development environment.
• Good analytical and debugging skills, with the ability to identify and resolve RTL and functional issues.
• Strong communication skills in English, both written and verbal, with the ability to document verification results clearly.
• Self‑motivated, detail-oriented, and able to work effectively both independently and within a team environment.

Responsibilities

• Understand DUT architecture, interfaces and functional requirements.
• Bring up formal verification testbench, implement constraints and properties, run proofs, generate coverage.
• Collaborate with verification and design teams to define verification test plans.
• Implement test cases, stimuli, and patterns to validate DUT and corner cases.
• Execute simulations and analyze RTL issues with waveform tools.
• Run and maintain regression suites across development cycles.
• Monitor and improve coverage metrics for verification closure.
• Document test cases and results to support sign-off.
• Contribute to automation scripts and Verification IP to boost productivity.

Skills

RTL design

AMBA protocols

RTL simulation

SystemVerilog & UVM

Formal verification

Linux scripting

Git/SVN

Debugging

English communication

Self-motivation

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Synopsys

Cadence

Mentor Graphics

Palladium

HAPS

Zebu

Job description

About Bitdeer

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.

About Bitdeer

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.

Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence.

Headquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia.

Role Overview

We are seeking a talented Design Verification Engineer to join our IC development team and help ensure the functional correctness and performance of computer arithmetic IPs. In this role, you will work closely with design and verification teams to develop comprehensive verification environments, execute test plans, and contribute to high-quality IP and silicon through systematic and coverage-driven verification.

Job Summary

• Apply UVM (Universal Verification Methodology), SystemVerilog, Verilog, and SVA (SystemVerilog Assertions) languages in verification tasks.
• Develop and implement state-of-the-art verification methodologies, including UVM, C/C++, co-simulation, formal verification, system emulation, and mixed-mode simulation/emulation.
• Contribute to projects requiring advanced verification tools such as Palladium, HAPS, and Zebu platforms.
• Collaborate effectively within a team, ensuring high-quality deliverables.

Key Responsibilities

• Equipped with a strong understanding of the Design Under Test (DUT), including its architecture, interfaces, and functional requirements.
• Bring up formal verification testbench, implement constraints and properties, run proof and debug counter example, generate coverage report.
• Collaborate with verification and design engineers to define, review, and refine verification test plans based on design specifications.
• Implement test cases, stimulus, and test patterns to validate DUT functionality and corner cases.
• Execute simulations and analyze/debug RTL issues using waveform analysis and debugging tools.
• Run and maintain regression test suites to validate design changes and ensure design stability across development cycles.
• Monitor and improve functional and code coverage metrics, contributing to coverage-driven verification and verification closure.
• Document test cases, verification results, and coverage reports to support verification sign-off.
• Contribute to the development and maintenance of automation scripts, reusable verification components, and Verification IP (VIP) to enhance team productivity.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or currently pursuing the degree for entry-level roles).
• Solid understanding of digital logic design and RTL development using Verilog or other Hardware Description Languages (HDL).
• Proficiency with AMBA bus protocols (AXI, AHB, APB).
• Hands‑on experience with RTL simulation, debugging, and waveform analysis using industry‑standard EDA tools (e.g., Synopsys, Cadence, or Siemens EDA / Mentor).
• Proficiency with SystemVerilog and modern verification methodologies such as UVM.
• Proficiency with formal verification tools (VC Formal or JasperGold) and main applications (FPV, DPV, etc).
• Familiarity with Linux/Unix environments and scripting for automation (e.g., Bash, C Shell, Perl, or Python).
• Experience using version control systems such as Git or SVN in a collaborative development environment.
• Good analytical and debugging skills, with the ability to identify and resolve RTL and functional issues.
• Strong communication skills in English, both written and verbal, with the ability to document verification results clearly.
• Self‑motivated, detail-oriented, and able to work effectively both independently and within a team environment.

Preferred Qualifications

• Proven track record of contributing to production‑grade and silicon‑proven IPs;
• Experience with using AI Agent for verification productivity.
• Familiarity with RISC‑V processor architecture or CPU verification concepts.
• Experience with C/C++ programming for testbench development or verification utilities.
• Exposure to coverage‑driven verification and regression automation workflows.

What You Will Experience Working With Us

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start‑up spirit;
• Fast‑growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.

Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.