Senior SOC DFX RTL Design Engineer - Front-End Focus

AMD; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

AMD in Penang, Malaysia seeks an experienced engineer to drive defect-free DFX RTL design for next-gen processors. You will participate in front-end design/integration, collaborate with architecture, IP design and physical design teams to enable first-pass silicon success.

You will contribute to DFX feature bring-up, debugging, and pattern analysis while coordinating with cross-functional teams globally. A strong background in Verilog/SystemVerilog and scripting is preferred.

Qualifications

• Bachelors or Masters in computer or electrical engineering.
• Experience with DFX, JTAG/Scan, MBIST or related DFT techniques.
• Strong RTL and gate-level debugging in Verilog/SystemVerilog.

Responsibilities

• DFX design planning and implementation of DFX features (JTAG, Scan, Boundary Scan, Debug).
• Collaborate with CAD/IP teams on requirements, implementations and power scenarios.
• Coordinate with DFX verification for quality and robustness.
• Drive DFX initiatives and process development in the team.
• Provide technical support to cross-functional teams.
• Be a team player and collaborate across sites/timezones.

Skills

DFX design

RTL & gate-level debugging

C/C++/Python scripting

Cross-site collaboration

Education

Bachelor's or Master's in computer/ electrical engineering

Tools

Verilog simulator

VCS

Mentor Graphics TestKompress

Synopsys Tetramax/DFTMAX

Job description

AMD in Penang, Malaysia seeks an experienced engineer to drive defect-free DFX RTL design for next-gen processors. You will participate in front-end design/integration, collaborate with architecture, IP design and physical design teams to enable first-pass silicon success.

You will contribute to DFX feature bring-up, debugging, and pattern analysis while coordinating with cross-functional teams globally. A strong background in Verilog/SystemVerilog and scripting is preferred.