Senior PCIe/HSIO Validation Engineer - Silicon Bring-Up

AMD; Malaysia; On-site; MYR 180,000 - 300,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD in Penang, Malaysia is seeking a Senior Product Development engineer to collaborate with design, validation and product engineering teams. You will drive technical decisions and be accountable for accurate, reliable results across projects with significant impact.

You will lead test strategy, pattern development, and interop testing for PCIe and high-speed interfaces, while guiding root-cause analysis and process improvements to optimize yield and cost.

Qualifications

• Experience delivering technically significant projects across engineering domains.
• Ability to influence decisions and own results.
• Strong scripting and automation mindset.
• Proficiency with Linux/Unix/Windows operating systems.

Responsibilities

• Collaborate with design, validation, and architecture teams on content coverage, test pattern development, validation, and debugging.
• Develop test program infrastructure incorporating best-known methods.
• Lead significant process changes and drive implementation across teams.
• Identify product improvements to reduce cost, improve yield, and resolve quality issues.
• Lead PCIe and high-speed I/O validation across the product roadmap, including test plan development and error handling.
• Drive root cause analysis on HSIO signal integrity and protocol failures using analyzers and scopes, distinguishing silicon vs board issues.
• Plan multi-vendor interoperability and PCI-SIG compliance testing and contribute to errata/known-issues documentation.

Skills

Perl

Ruby

Shell scripting

OS familiarity

Statistical analysis

Computer architecture

Education

CS/EE degree

Job description

AMD in Penang, Malaysia is seeking a Senior Product Development engineer to collaborate with design, validation and product engineering teams. You will drive technical decisions and be accountable for accurate, reliable results across projects with significant impact.

You will lead test strategy, pattern development, and interop testing for PCIe and high-speed interfaces, while guiding root-cause analysis and process improvements to optimize yield and cost.