Senior Leadframe & Substrate Package Designer (Power)

Carsem (M) Sdn. Bhd; Ipoh; On-site; MYR 80,000 - 120,000; Full time

Benefits offered by this job

Medical

Education support

Dental

Parking

Medical for immediate family members

Car subsidy

Job summary

Carsem (M) Sdn. Bhd. is seeking a season lead semiconductor package design engineer to lead leadframe and substrate design, simulations, and DFM/DFT rule development for power discrete packaging.

The role involves cross-functional collaboration with assembly, QA and tooling vendors to ensure reliability and cost targets. Responsibilities include 3D mechanical modeling, GD&T application, thermal/mechanical analysis, FEA, and customer-facing technical reviews.

Qualifications

• Minimum 7+ years hands-on experience in Leadframe & Substrate Design within Power Discrete (QFN, DFN, Clip-bond).
• Specialized Power Module Design experience is a strong plus.
• Proficient CAD & simulation tools: SolidWorks/AutoCAD/Creo and FEA/multiphysics suites (Ansys/COMSOL).
• Deep mastery of GD&T, DFM/DFT, thermal/electrical modeling, and tolerance analysis.
• Fabrication knowledge: sheet metal fabrication, stamping, etching, welding, riveting.
• Excellent technical communication for customer-facing reviews.

Responsibilities

• Design and 3D mechanical modeling of leadframes and substrates for power packaging.
• Apply GD&T for sub-micron precision in critical components.
• Perform thermal mechanical analysis and electrical parasitic simulations for high-power performance.
• Conduct robust FEA to mitigate early design risks (stress, warpage, thermal management).
• Develop and update internal design rules; incorporate DFM and DFT principles early.
• Lead design reviews and engage with customers and partners throughout projects.

Skills

Leadframe & Substrate Design

Power Discrete

GD&T

FEM/Multiphysics

DFM/DFT

Thermal/Electrical modeling

Customer-facing communication

Tools

SolidWorks

AutoCAD

Creo

Ansys

COMSOL

Job description

Carsem (M) Sdn. Bhd. is seeking a season lead semiconductor package design engineer to lead leadframe and substrate design, simulations, and DFM/DFT rule development for power discrete packaging.

The role involves cross-functional collaboration with assembly, QA and tooling vendors to ensure reliability and cost targets. Responsibilities include 3D mechanical modeling, GD&T application, thermal/mechanical analysis, FEA, and customer-facing technical reviews.