Senior IP Quality Engineer - Ecosystem Validation

GlobalFoundries inc.; George Town; On-site; MYR 180,000 - 260,000; Full time

Job summary

GlobalFoundries in Penang, Malaysia invites an expert Principal Engineer to lead IP quality assurance for ecosystem IP libraries. You will verify IP deliveries, issue approvals or non-conformances, and ensure convergence with PDK updates and tape-out schedules.

Strong Verilog/SystemVerilog and verification experience are essential to drive high-quality IP for customers. The role requires a minimum of 10 years in IC design, hands-on debugging across CV/DFT, and collaboration with external IP

Qualifications

• Bachelor/Master Degree in Electrical/Electronics Engineering or equivalent.
• Minimum 10 years of working experience in IC design field.
• Strong IP QA experience and ability to certify IP quality against QA checklist.
• Familiarity with PDK updates, silicon deliverables, and tape-out cycles.

Responsibilities

• Perform IP QA against predefined QA checklist and cycle time commitments.
• Issue certificate of approval or non-conformance for IP deliveries.
• Qualify IP merge kit to support customer tape-out and update IP Catalog.
• Define test cases for IP qualification and regression; maintain QA docs.
• Conduct IP regression (DRC/LVS/DFM, PEX, Spice) against criteria and timelines.
• Coordinate with stakeholders to drive IP issues to closure and document outcomes.
• Assist with scripting/automation to improve QA throughput and process.

Skills

SystemVerilog

ASIC verification

DFT/ATPG

Cadence tools

Scripting

Education

Electrical/Electronics Eng

Tools

Cadence

Verilog Sim

DFT Tools

Job description

GlobalFoundries in Penang, Malaysia invites an expert Principal Engineer to lead IP quality assurance for ecosystem IP libraries. You will verify IP deliveries, issue approvals or non-conformances, and ensure convergence with PDK updates and tape-out schedules.

Strong Verilog/SystemVerilog and verification experience are essential to drive high-quality IP for customers. The role requires a minimum of 10 years in IC design, hands-on debugging across CV/DFT, and collaboration with external IP