Senior Engineer, IO/ESD Design Support

Sinergia Talents; Kuching; On-site; MYR 100,000 - 201,000; Full time

Job summary

Sinergia Talents is seeking a Senior Engineer to support IO/ESD design, focusing on digital, RF and HV I/O libraries and ESD protection structures. You will contribute to conception, design, maintenance and evolution of ESD protection and IO pad libraries.

The role involves implementing protection concepts, developing pad cell designs, and producing front-end/back-end views, while documenting results. A multinational team environment and strong communication in German and English are required.

Qualifications

• Bachelor's degree in Electrical Engineering or comparable discipline.
• Graduate applications welcome; relevant work experience is a plus.
• Experience in electronic ASIC design (design, simulation, layout, verification) using EDA tools like Cadence/Mentor is a plus.
• Strong teamwork and collaboration in a multinational, multisite team.
• Good communication skills with written and spoken German and English.

Responsibilities

• Implement state-of-the-art ESD and latch-up protection concepts.
• Develop digital, RF or HV I/O library concepts including ESD-friendly pad cell design.
• Generate front-end and back-end views for I/O pad libraries.
• Apply layout best practices to optimize I/O pad cell performance within minimal area.
• Perform I/O pad library physical verification, characterization and documentation.

Skills

Teamwork & collaboration

Communication skills

German language

English language

Independent & structured work

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Job description

About the job Senior Engineer, IO/ESD Design Support

You will be part of a team responsible for I/O IP development focused on digital I/O libraries, RF I/O libraries and HV ESD protection. You will have the responsibility for the conception, design, maintenance, and further development of ESD protection structures and IO pad libraries.

Your Role:

• Implement state of the art ESD and latch-up protection concepts.
• Development of the digital, RF or HV I/O library concept including considerations for ESD and latch-up robust pad cell design.
• Generate front-end and back-end views for I/O pad libraries.
• Apply layout best practice to get the most optimal performance I/O pad cell design within the minimal area.
• I/O pad library physical verification, characterization, and documentation.

Your Profile:

• Bachelors degree in electrical engineering or a comparable discipline.
• Applications from graduates are welcome, relevant work experience is an advantage.
• Experience in electronic ASIC design (incl. design, simulation, layout, and verification) using EDA environments such as Cadence, Mentor etc. is welcome.
• Teamwork and collaboration skills, working within multinational, multisite team.
• You are reliable and independent, structured, and enthusiastic in your way of work.
• Good communication skills, good written and spoken knowledge of German and English language round up your profile.