Senior Engineer

LanceSoft, Inc.; Penang; On-site; MYR 180,000 - 270,000; Full time

Job summary

LanceSoft, Inc. in Penang seeks a Senior Engineer with deep ASIC/SoC expertise, focusing on synthesis, STA, DFT, and timing constraints. You will drive timing closure, ECO handling, and constraint validation while collaborating with RTL, Physical Design, and DFT teams.

This onsite 1-year contract may extend, requiring strong scripting and EDA tool experience. Qualified candidates have 5+ years in semiconductor/ASIC/SoC and hold a relevant engineering degree, with hands-on experience in DC,

Qualifications

• 5+ years of semiconductor/ASIC/SoC experience.
• Bachelor’s or Master’s degree in Engineering.
• Strong scripting skills in TCL, Perl, and/or Python.
• Experience writing timing constraints for Synthesis, STA, and Physical Design.
• Hands-on experience with ECOs and LEC.

Responsibilities

• Perform Synthesis, LEC, Low-Power Checks, Memory BIST insertion, and Constraints Validation.
• Collaborate with RTL Design, Physical Design, and DFT teams to identify and resolve synthesis, timing, and constraint-related issues early.
• Run and analyze RTL Lint, CLP, BIST, DFT insertion, and related implementation flows.
• Perform Full-Chip, Subsystem, and Block-Level STA.
• Develop and maintain TCL scripts for design implementation, analysis, and debugging.
• Work hands-on with EDA tools including Design Compiler (DC), Genus, Fusion Compiler, PrimeTime, Tempus, Formality, and Conformal.
• Handle ECOs and Logic Equivalence Checking (LEC).
• Mentor and train team members on early-stage implementation flows, tools, and best practices.
• Work independently with Design, DFT, and Physical Design teams to ensure successful netlist delivery and timing constraint validation.

Skills

ASIC/SoC

Synthesis

STA

DFT

Timing constraints

TCL scripting

Perl/Python scripting

Team mentoring

RTL/PD collaboration

Education

Bachelor’s or Master’s degree in Engineering

Tools

Design Compiler

Genus

Fusion Compiler

PrimeTime

Tempus

Formality

Conformal

Job description

Contract: 1 Year (Extendable)

Experience: 5+ Years

Work Type: Onsite

We are looking for an experienced Senior Engineer with strong expertise in ASIC/SoC implementation, Synthesis, STA, LEC, DFT, and timing constraints to join our engineering team in Penang.

Key Responsibilities

• Perform Synthesis, LEC, Low-Power Checks, Memory BIST insertion, and Constraints Validation.
• Collaborate with RTL Design, Physical Design, and DFT teams to identify and resolve synthesis, timing, and constraint-related issues early.
• Run and analyze RTL Lint, CLP, BIST, DFT insertion, and related implementation flows.
• Perform Full-Chip, Subsystem, and Block-Level STA.
• Develop and maintain TCL scripts for design implementation, analysis, and debugging.
• Work hands-on with industry-standard EDA tools including Design Compiler (DC), Genus, Fusion Compiler, PrimeTime, Tempus, Formality, and Conformal.
• Handle ECOs and Logic Equivalence Checking (LEC).
• Mentor and train team members on early-stage implementation flows, tools, and best practices.
• Work independently with Design, DFT, and Physical Design teams to ensure successful netlist delivery and timing constraint validation.

Required Qualifications

• Bachelor’s or Master’s degree in Engineering.
• 5+ years of relevant semiconductor/ASIC/SoC experience.
• Strong understanding of Synthesis methodologies and industry-standard EDA tools.
• Hands-on experience writing timing constraints for Synthesis, STA, and Physical Design.
• Experience performing Full-Chip and Block-Level STA using PrimeTime or Tempus.
• Strong scripting skills in TCL, Perl, and/or Python.
• Ability to work independently with Design, DFT, and Physical Design teams.
• Hands-on experience with ECOs and Logic Equivalence Checking (LEC).

Preferred Qualifications

• Familiarity with DFT methodologies.
• Knowledge of power estimation using vectors and UPF (Unified Power Format).
• Familiarity with additional EDA tools and implementation flows.
• Experience with RTL Development or Physical Design is an added advantage.