Senior E-Core CPU Layout Engineer - Hybrid

Intel Corporation; Penang; Híbrido; MYR 180.000 - 280.000; Jornada completa

Descripción de la vacante

Intel Corporation in Penang seeks an experienced E-Core (Atom) CPU Layout Design Engineer to shape the physical layout of Atom processors, focusing on analog blocks, digital designs, and memory compilers. You will implement custom layouts and ensure design rule compliance, reliability, and integration with SoC standards.

You will collaborate with circuit designers and cross-site teams, using advanced EDA tools to drive productivity, quality, and innovative layout solutions for high-performance

Formación

• Bachelor's or Master's degree in Electronics/Microelectronics Engineering, Computer Engineering, or related discipline.
• 9+ years of experience in layout design.
• Proficiency in VLSI and CMOS logic circuit design.
• Programming skills in UNIX shell scripting, TCL, and Perl.

Responsabilidades

• Drive custom layout design for memory compilers, custom IPs, and partitions.
• Perform physical array planning, area optimization, and critical wire analysis.
• Conduct complete layout verification including design rule compliance and reliability checks.
• Utilize custom autorouters and placers for layout construction and innovate methods to improve productivity.
• Collaborate with circuit design engineers to assess feasibility and implement enhancements.
• Troubleshoot design, tool flow, and methodology issues for seamless implementation.
• Partner with cross-site teams to align on design strategies and project consistency.

Conocimientos

VLSI

CMOS design

UNIX shell scripting

TCL

Perl

Educación

Bachelor's or Master's degree in Electronics/Microelectronics Engineering or Computer Engineering

Descripción del empleo

Intel Corporation in Penang seeks an experienced E-Core (Atom) CPU Layout Design Engineer to shape the physical layout of Atom processors, focusing on analog blocks, digital designs, and memory compilers. You will implement custom layouts and ensure design rule compliance, reliability, and integration with SoC standards.

You will collaborate with circuit designers and cross-site teams, using advanced EDA tools to drive productivity, quality, and innovative layout solutions for high-performance