Senior Backend Physical Verification Engineer Leader

TalentWork; George Town; On-site; MYR 150,000 - 200,000; Full time

Job summary

A leading integrated circuit technology company in Penang is seeking a Senior Backend Physical Verification Engineer Leader to establish and lead the physical verification team. Candidates should have over 5 years of experience, expertise in EDA tools, and leadership skills. This pioneer role offers competitive compensation and the chance to shape semiconductor technology in a new facility.

Benefits

Competitive compensation package

Career growth opportunities

Collaborative and innovative work environment

Qualifications

• More than 5 years of experience in physical verification, with demonstrated leadership experience.
• Strong scripting skills with Tcl/Perl; familiarity with Python is a plus.
• Spoken fluency in Mandarin is required.

Responsibilities

• Lead and mentor a team of physical verification engineers.
• Develop and implement full chip physical verification methodologies.
• Perform and oversee DRC/LVS/ERC checks using industry-standard EDA tools.

Skills

Leadership

Physical verification flow

Scripting (Tcl/Perl)

EDA tools (Calibre, Virtuoso, ICC2, Innovus)

Education

Bachelor's or Master's degree in Electrical and Electronics Engineering, Computer Science, or related fields

Job description

Job Openings Senior Backend Physical Verification Engineer Leader

About the job Senior Backend Physical Verification Engineer Leader

Our client is a leading integrated circuit technology company specializing in IP/SOC solutions, system customisation design, and design services. With office locations in China and Silicon Valley, they are expanding operations to Penang, Malaysia, and seeking pioneering talents to join their new plant.

Position Overview:

We are seeking a Senior Backend Physical Verification Engineer Leader who will play a crucial role in establishing and leading the physical verification team in Penang. The ideal candidate will have extensive experience in full chip level physical verification flow, both at block and sub-hierarchical levels. This role requires expertise in resolving and fixing violations related to Antenna, EM, DRC, LVS, and backend notation.

Key Responsibilities:

• Lead and mentor a team of physical verification engineers.
• Develop and implement full chip physical verification methodologies.
• Perform and oversee DRC/LVS/ERC checks using industry-standard EDA tools (ICC2, Innovus, Calibre, Virtuoso).
• Collaborate with design and CAD teams to resolve physical verification issues efficiently.
• Ensure compliance with company standards and industry best practices.

Requirements:

• More than 5 years of experience in physical verification, with demonstrated leadership experience.
• Proficiency in EDA tools such as Calibre, Virtuoso, ICC2, and Innovus.
• Strong scripting skills with Tcl/Perl; familiarity with Python is a plus.
• Bachelor's or Master's degree in Electrical and Electronics Engineering, Computer Science, or related fields.
• Spoken fluency in Mandarin is required for effective communication with headquarters and team members (read / write a plus)

Why Join Us:

• Opportunity to be part of a pioneering team in a new facility.
• Competitive compensation package and benefits.
• Career growth opportunities in a rapidly expanding company.
• Collaborative and innovative work environment.

If you are a dynamic leader with a solid background in backend physical verification engineering and are excited about shaping the future of semiconductor technology in Penang, we encourage you to apply. Join us and contribute to our mission of delivering cutting-edge IC solutions to global markets.