Senior Application Engineer: FPGA/ASIC Design & Escalation Lead

Altera; Penang; On-site; MYR 180,000 - 280,000; Full time

Job summary

Altera in Penang is seeking a Staff Application Engineer to join the Worldwide Regional Applications group, enabling next‑gen designs across Agilex devices. You will collaborate with R&D teams and customers to drive design success in a fast-paced environment.

Responsibilities include handling escalations, aiding field teams and distributors with design improvements, and developing collateral and reference designs.

Qualifications

• BS/MS/PhD in Electronics, Electrical or Software Engineering with 10+ years in Architecture, Design or implementation in 5G/DSP.
• Excellent working knowledge of RTL-based design flows and expectations.
• Good knowledge of the FPGA/ASIC design process and timing closure.
• Familiarity with Quartus tool and design methodologies.
• Strong communication and teamwork across sites and domains.

Responsibilities

• Handle key customer escalations from analysis to closure.
• Collaborate with field teams and distributors to improve customer designs and experience.
• Participate in development projects with international cross-organizational teams.
• Develop and deliver training materials on new features and methodologies.
• Contribute to internal communication across regions and teams.

Skills

RTL-based design flows

Problem Solving

Technical Communication

Teamwork

Education

BS/MS/PhD in Electronics, Electrical or Software Engineering

Tools

Quartus

Job description

Altera in Penang is seeking a Staff Application Engineer to join the Worldwide Regional Applications group, enabling next‑gen designs across Agilex devices. You will collaborate with R&D teams and customers to drive design success in a fast-paced environment.

Responsibilities include handling escalations, aiding field teams and distributors with design improvements, and developing collateral and reference designs.