Senior Application Engineer – FPGA/ASIC, 5G & DSP

Altera Corporation; Kuala Lumpur; Sur place; MYR 180 000 - 260 000; Plein temps

Résumé du poste

Altera is seeking a Staff Application Engineer in Penang to work with a seasoned Applications Engineering team on next-generation designs across FPGA/ASIC platforms. You will support customer escalations, collaborate with field teams, and contribute to international projects while developing training materials and collateral.

The role requires a strong background in RTL-based design, FPGA/ASIC design processes, and timing closure, with excellent communication and teamwork across sites.

Qualifications

• BS/MS/PhD in Electronics, Electrical or Software Engineering with 10+ years in architecture, design or implementation in 5G/DSP.
• Excellent knowledge of RTL-based design flows and expectations.
• Good understanding of FPGA or ASIC design process and tool flow with timing closure experience.
• Experience with Quartus and related design methodologies.
• Strong problem solving and clear technical communication across teams.

Responsabilités

• Handle key customer escalations from analysis to closure.
• Collaborate with field teams and distributors to improve designs and customer experience.
• Participate in international cross-organizational projects and develop collateral.
• Develop and deliver training materials on new features and methodologies.
• Stay current with industry approaches and best practices.

Connaissances

RTL-based design flows

FPGA/ASIC design process

Timing closure

Problem solving

Technical communication

Teamwork across sites

Formation

BS/MS/PhD in Electronics, Electrical or Software Engineering

Outils

Quartus tool

Description du poste

Altera is seeking a Staff Application Engineer in Penang to work with a seasoned Applications Engineering team on next-generation designs across FPGA/ASIC platforms. You will support customer escalations, collaborate with field teams, and contribute to international projects while developing training materials and collateral.

The role requires a strong background in RTL-based design, FPGA/ASIC design processes, and timing closure, with excellent communication and teamwork across sites.