Staff Applications Engineer — 5G FPGA/ASIC Design Expert

Altera

Bayan Lepas

On-site

MYR 180,000 - 240,000

Full time

46 hours ago
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Job summary

Altera in Penang, Malaysia, is seeking an experienced Staff Application Engineer to join the Worldwide Regional Applications group. You will handle customer escalations, collaborate with field teams and distributors, and contribute to cross-organizational projects with reference designs and training materials.

The role emphasizes deep RTL/FPGA/ASIC design knowledge, strong communication, and teamwork across sites.

Qualifications

  • BS/MS/PhD in Electronics, Electrical or Software Engineering with minimum 10 years of relevant experience in Architecture, Design, or implementation experience in 5G, DSP.
  • Experience in Architecture, Design, or implementation in 5G and DSP; IEEE standard development is a plus.

Responsibilities

  • Handle key customer escalations from analysis to closure.
  • Work closely with field team and distributors to help customers improve designs and experiences.
  • Participate in development projects, possibly in international cross-organizational teams; may generate collateral and reference designs.
  • Develop and deliver training materials on new features and methodologies.
  • Develop strong local and international intra- and inter-organizational communication in a team-based environment.
  • Stay current with industry approaches, algorithms, and practices and propose internal use.

Skills

RTL-based design flows
FPGA/ASIC design process
Quartus tool
Problem Solving
Technical Communication
Teamwork

Education

BS/MS/PhD in Electronics, Electrical or Software Engineering

Tools

Quartus tool

Job description

Altera in Penang, Malaysia, is seeking an experienced Staff Application Engineer to join the Worldwide Regional Applications group. You will handle customer escalations, collaborate with field teams and distributors, and contribute to cross-organizational projects with reference designs and training materials.

The role emphasizes deep RTL/FPGA/ASIC design knowledge, strong communication, and teamwork across sites.

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