Post-Silicon Memory Validation Staff Engineer

ThunderSoft; Penang; On-site; MYR 50,000 - 80,000; Full time

Job summary

A technology firm in Malaysia, Penang, is seeking a Senior Electrical Test and Debug Engineer. This role involves providing technical leadership in DDR interface feature validation and debugging issues within the memory subsystem of new processors. Ideal candidates will have strong hands-on experience with electrical test plans, excellent communication skills, and familiarity with lab equipment like oscilloscopes. Knowledge of scripting in Python or similar languages is a plus, alongside experience in Linux environments.

Qualifications

• Strong technical background on DDR interface.
• Extensive hands-on experience in debugging I/O interfaces.
• Experience with electronic components like uProcessors.

Responsibilities

• Provide DDR technical leadership in test & validation features.
• Interact with silicon design in test execution & debug.
• Write comprehensive electrical & functional test plans.

Skills

Technical expertise in DDR interface

Communication skills

Debugging I/O interfaces

Scripting knowledge (Python, Ruby, Perl)

Tools

Oscilloscopes

Logic analyzers

Protocol analyzers

Job description

Processor silicon DDR interface feature enablement, electrical test and debug engineer. In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & feature enable, & debugs electrical issues in the memory sub-system of new processors.

Overview

The person needs to be well self-motivated for deliveries and innovation, strong technical background on DDR interface, also with good communication skills.

KEY RESPONSIBILITIES

• Provides DDR technical leadership in the development of new test & validation features
• Closely interacts with silicon design (DRAM controller and memory Phy) in test execution & debug, as well as in feature definition for future product generation
• Writes comprehensive electrical & functional test plans for the memory validation of processors
• Executes electrical & functional test plans for AMD processors using hardware & software validation tools, oscilloscopes, & logic analyzers.
• Debug of electrical & functional issues of the memory sub-system of new processors
• Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors.

PREFERRED EXPERIENCE

• Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR5(4)/LPDDR5(4) Memory test experience on electronic components such as uProcessors would be considered a big plus.
• Requires extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR
• Familiar with DDR signal measurement, reading schematics and layout documentation
• Requires good written and oral communication skills
• Familiar with Python, Ruby, Perl language.
• Working knowledge of lab equipment such as oscilloscopes, logic analyzers and protocol analyzers
• Self-organizing and the ability multitask based on priorities
• Scripting and automation tool development is a plus.
• Linux environment validation or development experience is also a great plus