Post-Silicon FPGA Validation Engineer (MCP)

Altera Corporation; George Town; On-site; MYR 70,000 - 110,000; Full time

Job summary

Altera Corporation in Penang, Malaysia seeks a Product Validation Engineer to join its post-silicon validation team. You will validate timing and power models for MCP FPGAs, develop validation patterns, and drive ATE-based characterization to improve silicon yield and speed binning.

You will collaborate with global designers and test teams, bridging pre-silicon models with real hardware performance, and contribute to robust validation plans and data-driven quality improvements.

Qualifications

• BS or MS in Electrical/Electronic Engineering or related field with 3 to 6 years of hands-on industry experience in post-silicon validation, test engineering, or hardware characterization.
• Experience in static/dynamic power measurement, timing characterization, and power domain analysis for complex ICs or FPGAs.
• Hands-on experience with ATE tester platforms and scripting languages (Python, Perl, or Tcl) for automated tests and data analysis.

Responsibilities

• Power & Timing Validation Execution: measure static/dynamic power, power domains, and timing parameters.
• Validation Pattern & Test Development for MCPs and core logic circuits.
• ATE & Platform Characterization on various tester platforms and bench setups.
• Simulation-to-Silicon Correlation between pre-silicon models and hardware results.
• Data Analysis & Binning Support to optimize speed binning and yield.
• Cross-Functional Collaboration with global chip designers and test teams.

Skills

Power & Timing Validation

Data analysis

Scripting (Python/Perl/Tcl)

FPGA & Digital Logic Knowledge

Education

BS/MS in Electrical/Electronic Engineering

Tools

ATE tester platforms

Python

Perl

Tcl

Job description

Altera Corporation in Penang, Malaysia seeks a Product Validation Engineer to join its post-silicon validation team. You will validate timing and power models for MCP FPGAs, develop validation patterns, and drive ATE-based characterization to improve silicon yield and speed binning.

You will collaborate with global designers and test teams, bridging pre-silicon models with real hardware performance, and contribute to robust validation plans and data-driven quality improvements.