FPGA Post-Silicon Validation Engineer

Altera; Penang; On-site; MYR 60,000 - 90,000; Full time

Job summary

Altera in Penang, Malaysia is seeking a post-silicon validation engineer to drive timing and power model validation for MCP FPGA devices. You will develop validation patterns, run ATE-based tests, and correlate results with pre-silicon models.

You will work with global chip designers and test teams to optimize silicon yield and speed binning, applying Python/Perl/Tcl for automation and data analysis.

Qualifications

• BS or MS in Electrical/Electronic Engineering with 3–6 years of hands-on post-silicon validation or hardware characterization.
• Experience in static/dynamic power measurement and timing characterization.
• Proficiency with scripting languages (Python, Perl, Tcl) for automation and data analysis.
• Knowledge of MCP packaging and FPGA architectures.
• Strong analytical and problem-solving skills with data analysis tools.

Responsibilities

• Develop and execute post-silicon validation plans for power and timing.
• Create, optimize, and debug FPGA validation patterns for MCPs and core logic.
• Drive ATE-based characterization and bench setup for volume bring-up.
• Analyze silicon data to validate and correlate pre-silicon models.
• Conduct deep-dive data analysis to support speed and power binning strategies.
• Collaborate with chip designers, software model engineers, and test teams to resolve silicon issues.

Skills

Power validation

Timing analysis

Statistical data analysis

FPGA knowledge

Digital logic

Analytical mindset

Education

BS in Electrical/Electronic Engineering

MS in Electrical/Electronic Engineering

Tools

ATE platforms

Python

Perl

Tcl

Job description

Altera in Penang, Malaysia is seeking a post-silicon validation engineer to drive timing and power model validation for MCP FPGA devices. You will develop validation patterns, run ATE-based tests, and correlate results with pre-silicon models.

You will work with global chip designers and test teams to optimize silicon yield and speed binning, applying Python/Perl/Tcl for automation and data analysis.