Hybrid E‑Core CPU Physical Design Engineer

Intel Corporation; Kuala Lumpur; Hybrid; MYR 170,000 - 230,000; Full time

Job summary

Intel Corporation in Malaysia, Penang, is seeking an experienced E-core CPU Physical Design Engineer to join a high-performance team. You will work on implementation of CORE IP blocks, from synthesis through post-layout verification and tapeout, collaborating with RTL and circuit teams to meet timing and power targets.

The role emphasizes strong analytic and communication skills, with hybrid work options and a focus on floorplanning, timing closure, and low-power design techniques for

Qualifications

• Must have BS or MS in Electrical or Computer Engineering.
• Minimum 6 years of CPU physical design and timing verification experience.
• Experience with synthesis/APR flows on high-frequency designs and Tcl scripting.
• Knowledge of floorplanning, physical design, timing closure, DRC/LVS, and IR checks.

Responsibilities

• Logic synthesis and place & route for CORE IP blocks.
• Floor-planning and routing studies; block/sub-system timing analysis.
• Work on low power techniques and power reduction in sub-systems.
• Physical verification closure of block/sub-system.
• Write scripts for data analysis and recipe creation.
• Collaborate with micro-architecture, RTL and circuit teams to meet targets.
• Contribute in a high-performing team under aggressive schedules.

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Fusion Compiler

DCT

DCE

ICC2

RedHawk

ICV

Conformal

Calibre

PrimeTime

StarRCXT

Cadence Tools

Job description

Intel Corporation in Malaysia, Penang, is seeking an experienced E-core CPU Physical Design Engineer to join a high-performance team. You will work on implementation of CORE IP blocks, from synthesis through post-layout verification and tapeout, collaborating with RTL and circuit teams to meet timing and power targets.

The role emphasizes strong analytic and communication skills, with hybrid work options and a focus on floorplanning, timing closure, and low-power design techniques for