Senior CPU Verification Engineer — Core Microarchitecture

Intel Corporation; Kuala Lumpur; On-site; MYR 150,000 - 230,000; Full time

Job summary

Intel Corporation in Penang, Malaysia, is seeking a Senior Core Design Verification Engineer to drive verification of CPU microarchitectures. You will create verification plans, build test benches, and run system-level simulations to validate functionality, power, and timing while debugging presilicon issues.

You will collaborate with CPU architects, RTL and physical design teams to optimize verification strategies and ensure high-quality silicon deliverables.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 4 years of experience in ASIC or FPGA design verification, preferably CPU or E-Core designs.
• Proficiency in SystemVerilog and UVM verification languages.
• Strong scripting and programming skills (e.g., Python, C/C++).

Responsibilities

• Perform functional verification of CPU logic to ensure designs meet specification requirements.
• Develop and execute IP verification plans, test benches and environments for CPU microarchitecture coverage.
• Define and run system simulation models to verify design functionality, analyze power and timing, and uncover bugs.
• Collaborate with CPU architects, RTL developers and physical design teams to optimize verification targets.
• Document verification plans and lead technical reviews with design and architecture teams.

Skills

Verification planning

IP verification

Programming scripting

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in Electrical/Computer Engineering or related field

PhD (preferred)

Tools

SystemVerilog

UVM

Python

C/C++

Job description

Intel Corporation in Penang, Malaysia, is seeking a Senior Core Design Verification Engineer to drive verification of CPU microarchitectures. You will create verification plans, build test benches, and run system-level simulations to validate functionality, power, and timing while debugging presilicon issues.

You will collaborate with CPU architects, RTL and physical design teams to optimize verification strategies and ensure high-quality silicon deliverables.