Hybrid Clock Design Engineer for CPUs | Timing & Power

Intel Corporation; Kuala Lumpur; Hybrid; MYR 180,000 - 300,000; Full time

Job summary

Intel Corporation in Penang, Malaysia, seeks a skilled CPU Clock Design Engineer to join a hybrid team. You will design, implement, and optimize clock distribution networks for high-performance CPUs and SoCs, contributing to clock architecture and CTS methodologies.

You will perform timing analyses, develop library cells, and create automation to boost design productivity. The role requires strong problem-solving, ownership, and collaboration across architecture, design, and EDA teams, with

Qualifications

• BS or MS in Electrical or Computer Engineering.
• 6+ years in CPU clock design and timing verification.
• Experience with multi-voltage high-frequency designs.
• Proficiency in Tcl scripting.
• Familiarity with CTS, DRC/LVS, IR and electromigration checks.

Responsibilities

• Design, implement, and optimize clock distribution networks for high-performance CPUs/SoCs.
• Contribute to clock architecture development and CTS methodologies.
• Perform timing analysis and support timing closure across designs.
• Develop custom circuits and clock-related library cells.
• Create automation using scripting to improve productivity.
• Collaborate with architecture, physical design, validation, and EDA teams.
• Support debug, validation, and optimization throughout development.

Skills

CPU Clock Design

CPU physical design

Timing verification

Tcl scripting

Noise & cross-talk analysis

Floorplanning

Formal equivalence & LVS

IR & electromigration checks

Education

BS or MS in Electrical Engineering or Computer Engineering

Tools

Fusion Compiler

DCT

DCE

ICC2

RedHawk

ICV

Conformal

Calibre

PrimeTime

StarRCXT

Cadence tools

Job description

Intel Corporation in Penang, Malaysia, seeks a skilled CPU Clock Design Engineer to join a hybrid team. You will design, implement, and optimize clock distribution networks for high-performance CPUs and SoCs, contributing to clock architecture and CTS methodologies.

You will perform timing analyses, develop library cells, and create automation to boost design productivity. The role requires strong problem-solving, ownership, and collaboration across architecture, design, and EDA teams, with