E-core CPU Clock Design Engineer

Intel Corporation; George Town; Hybrid; MYR 120,000 - 210,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Intel Corporation in Malaysia seeks an experienced CPU Clock Design Engineer to design, implement, and optimize clock distribution networks for high-performance CPUs and SoCs.

You will contribute to clock architecture, CTS methods, and timing closure while collaborating with architecture, design, and EDA teams. A hybrid on-site/off-site work model is offered in Malaysia.

Qualifications

• BS or MS in Electrical or Computer Engineering.
• Experience in CPU clock design and timing verification.
• Familiarity with clock distribution design and CTS methodologies.
• Proficiency in Tcl scripting and standard EDA flows.

Responsibilities

• Design, implement, and optimize clock distribution networks for CPU/SoC products.
• Contribute to clock architecture development and CTS methodologies.
• Perform timing analysis and support timing closure.
• Develop clock-related design solutions and library cells.
• Assess performance, power, area, and timing tradeoffs.
• Create automation to improve design productivity with scripting.

Skills

Clock design

Timing analysis

Synthesis

Tcl scripting

Power/Noise analysis

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Fusion Compiler

ICC2

Calibre

PrimeTime

Job description

Job Details

Job Description: Join a Team That Defines the Heartbeat of Next-Generation CPUs. Intel is seeking passionate engineers to help develop the clocking architecture that powers our next-generation CPU products. Whether you're a college graduate eager to launch your career or an experienced engineer ready to solve some of the industry's most complex technical challenges, you'll have the opportunity to work on cutting-edge semiconductor technologies that impact millions of devices worldwide. As a CPU Clock Design Engineer you will contribute to the design, implementation, analysis, and optimization of clock distribution networks that enable industry-leading performance, power efficiency, and product scalability.

What You'll Do

• Design, implement, and optimize clock distribution networks for high-performance CPU and SoC products.
• Contribute to clock architecture development and clock tree synthesis (CTS) methodologies.
• Perform timing analysis and support timing closure across complex semiconductor designs.
• Develop custom circuits, library cells, and clock-related design solutions.
• Analyze performance, power, area, and timing tradeoffs to improve product efficiency.
• Create automation solutions using scripting and programming languages to improve design productivity.
• Collaborate closely with architecture, design, physical implementation, validation, and EDA teams.
• Support debug, validation, and optimization activities throughout the product development lifecycle.
• Drive technical issues to closure while maintaining high-quality engineering standards.
• Influence future methodologies, design flows, and clocking technologies.

Behavioral Traits We Are Looking For

• Strong ownership and accountability for technical deliverables.
• Curiosity and passion for solving complex engineering challenges.
• Effective problem-solving and analytical thinking skills.
• Ability to collaborate across multiple engineering disciplines.
• Strong communication skills with both technical and non-technical stakeholders.
• Adaptability and willingness to learn new tools, technologies, and methodologies.
• Ability to balance multiple priorities in a fast-paced environment.
• Continuous focus on quality, execution, and innovation.

Qualifications

Minimum qualifications:

• Must have either BS or MS in Electrical Engineering or Computer Engineering.
• Minimum 6 year of experience in:
• CPU Clock Design.
• CPU physical design and timing verification.
• Synthesis/APR flows on multi voltage high frequency designs including custom polygon editing.
• Tcl scripting.
• Noise, cross-talk, OCV analysis.
• Floorplanning and physical design and timing closure.
• Formal equivalence, DRC/LVS, IR and electro-migration checks.

Preferred qualifications:

• 7+ years of experience with the above skill sets.
• Experience with Fusion Compiler, DCT, DCE, ICC2, RedHawk, ICV, Conformal, Calibre, PrimeTime, StarRCXT.
• Cadence Tools Experience Not a Must But Preferred.

Job Type

Experienced Hire

Shift

Shift 1 (Malaysia)

Primary Location

Malaysia, Penang

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.